Chakradhar Rao

Project :

Description:

Technology: 3 nm.

Instance Count: 2.4M

Frequency: 2 GHz

Macro Count: 155.

Roles and Responsibilities

• Coordinated with back-end activities like placement, CTS, routing, congestion avoidance, and DRC and LVS checking, as well as the sign-off cycle.
• Carried out ECOs by analyzing schematic changes and performing necessary modifications in the existing layout.

Owning PnR, and timing closure, ECOs.

Tools Used: Innovus, tweaker.

Client: Qualcomm

project:

Description:

Instance count: 1.4M, 900k, 750k.

macro count: 22, 43, 55

Frequency: 800 MHz.

Technology: 5 nm

Tool used: ICC2, prime time.

Responsibilities:

Worked on three blocks for block-level floorplan to GDSII implementation of timing-critical design, along with Ecos and Caliber.

Client: INTEL, Bangalore

Project:

Description:

Technology: 5 nm

Instance count: 1.5M.

Macro count: 377

Frequency: 1.39 GHz.

Roles and responsibilities :

Block Level RTL to GDSII implementation of timing, congestion-critical design, along with macro-dominant partitions.

PnR, Timing Fix, and Physical Verification, ECO, signoff.

Client: NVIDIA, Bangalore.

Project:

Description:

Technology: TSMC 7nm.

Instance count: 973K.

Macro count: 35

Frequency: 550 MHz.

Responsibilities:

Block-level floorplan to GDSII implementation of congestion and timing-critical design.

PnR, Timing Fix, and Physical Verification

Client: Intel, Bangalore.

Project:

Description:

Technology: INTEL 10nm++

Instance count: 1.1M, 455k.

macros:35 ,85

Frequency: 750, 800 MHz

Responsibilities:

Block-level floorplan to GDSII implementation of timing-critical design.

PnR, Timing Fix, and Physical Verification, ECO, caliber.

Client: INTEL, Bangalore.