Chandan Kumar
Bengaluru
Summary
Driving innovation in low power design, I contribute to the development of next-generation architecture. Leveraging my strong software development foundation, built over 7 years of delivering large-scale, complex projects in C/C++, I bring a unique perspective to the table. Previously, I played a key role in Mentor Graphics' Questa Power Aware Simulation team, where I honed my expertise in low power simulation. Now, I'm excited to apply my skills and experience to shape the future of semiconductor industry.
Overview
7
7
years of professional experience
Work History
Staff Engineer
SYNOPSYS India Pvt. Ltd.
Bangalore
03.2022 - Current
- Developing low power verification methodologies for Zebu Emulation.
Senior R&D Engineer
ANSYS Software Pvt. Ltd.
Noida
09.2021 - 02.2022
- Contributed to the design elaboration and synthesis stage for Power Artist tool.
Senior Member of Technical Staff
Mentor Graphics (India) Pvt. Ltd.
Noida
06.2018 - 08.2021
- Implemented new UPF constructs for low power simulation tool, Questa Sim
- Enhanced low power static checkers, significantly reducing timing for static analysis on big customer designs
- Implemented runtime retention checks for detecting incorrect retention behavior in power aware designs
- Optimized tool performance for specific in-house customer designs and overall enhanced accuracy and robustness by resolving customer and internal issues
Member of Technical Staff
Mentor Graphics (India) Pvt. Ltd.
Noida
08.2017 - 05.2018
- Gained proficiency in UPF principles by actively participating in trainings and conducting self-guided research.
- Implemented Tcl based query commands to efficiently retrieve information from the Power Aware Information Model Data Base (PA-IMDB)
- Streamlined tool functionality through the removal of redundancies.
Education
B.Tech & M.Tech - Electrical Engineering, Instrumentation & Signal Processing
Indian Institute of Technology, Kharagpur-W.B., India
12.2017
Skills
- C/C
- Algorithms
- Data Structures
- Design Patterns
- UPF
- Verilog/System Verilog/VHDL
- Power Aware Verification
Extracurricular Activities
Secured 5th place in Inter Hall Athletics competition (2015).
Part of bronze winning hockey team in Inter Hall hockey competition (2012-13).
Timeline
Staff Engineer
SYNOPSYS India Pvt. Ltd.
03.2022 - Current
Senior R&D Engineer
ANSYS Software Pvt. Ltd.
09.2021 - 02.2022
Senior Member of Technical Staff
Mentor Graphics (India) Pvt. Ltd.
06.2018 - 08.2021
Member of Technical Staff
Mentor Graphics (India) Pvt. Ltd.
08.2017 - 05.2018
B.Tech & M.Tech - Electrical Engineering, Instrumentation & Signal Processing
Indian Institute of Technology, Kharagpur-W.B., India
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