Chandrasekhar Kypa

Responsible for multiple projects for AMD VBU. Right from engineering proposals, staffing and delivering of projects while maintaining healthy profit margins. Delivered large scale programs including hardening of various high speed interfaces, compute and graphics IPs. Established competency centres to deliver complex IPs for the last 5 years. I was able to delivery 2 successfully RTL integration projects, established 3 large Physical Design Offshore Design Centre for AI Semiconductor giant.

• Responsible for defining strategies for business, hiring, staffing and performance management for Custom and Semicustom design practice business lines
• Responsible for revenue generation and profit margins in PD and DFT practice line
• Responsible for delivery of PD blocks for an AI chip.
• Tracking partitions releases for various full chip integration activities
• Driving reviews of complex partitions [routing/timing critical blocks]
• Interacting with technology/flow teams to ensure right environment is set.
• Hiring/staffing/risk management/vendor management to ensure smooth project execution.

• Responsible for delivering Complex SoC/IPs and services to one of Eximius biggest customers.
• Revamped Physical Verification Centre of Excellence (PV CoE) to deliver 10nm and 7nm block designs on short notice and with short turnaround time.
• Delivered 7nm Multi Die Interface IP for one of the critical programs: Team delivered hardened IP (RTL Modification, Synthesis, R&R. Timing Closure and Layout verification) for full SoC Integration.
• Delivering 10nm Multi Die interface with TSVs.
• Establishing processes to deliver high quality harden digital IPs for graphics chips.

• Responsible for establishing competency centers in the areas of Design Automation and Design Implementation.
• Develop and deliver and deploy Infineon Internal CAD flows
• Established teams to deliver PDKs, IO Cells, and PCB Components
• Established Automotive related Quality Standards in Design flows and prepared teams for Functional safety Audits like ISO26262... etc.
• Physical Design Methodologies and Design Implementation of Automotive Microcontrollers, Hearing Aid Device Drivers.
• Internal EDA software Development for Code Generation, Mask Preparation, and other automation solutions.
• Global EDA Licenses Management
• Setting up Emerging Technology Teams like IoT and Applied Machine Learning
• Last 7 years I have successfully hired and developed team leaders to manage operations independently.

• I was responsible for managing Physical design projects for Graphics products.
• Responsibilities were managing Full Chip Integration (GPU)
• Collaborating with the front-end team to freeze RTL and schedules
• Working with Technology team to finalize rule decks and technology file versions for Physical Verification.
• Physical IP Hardening
• People Management responsibility of 40 engineers per project.
• Qualified Tools and Methodologies for smooth execution of tape outs
• Drove the total checklist automation system.

• Built a design services team and deployed at four major customer sites.
• Drove close engagement in deploying Synopsys technology with major Networking/Wireless communication clients.
• Successfully delivered Physical Design (TSMC 40nm), Functional verification and DFT Consulting projects.
• Established Processor Competency Centre (PPC and ARM Core) in India to deliver Reference flows for integrating ARM/PPC into SOCs.

• Built a competent Circuit, Layout and Post-Silicon Validation team in the 1-year time frame during 2003.
• Delivered GPIO libraries on 130, 90 and 65nm technologies.
• Established Macro IO competency including ASIC style of IP implementation.
• Delivered Complex IO Phys including USB2.0 (complete) /DDR / PATA / MIPI.
• Established post-silicon validation lab and delivered validation services for multiple IO.
• Established robust QA mechanism to deliver first-pass silicon success.
• Fostered innovation; 5 Patent Applications and 2 papers have been filed by the team.

• Cell library Layout development for 180 and 130 nm.
• Library Characterization & View generation (Timing, Verilog & Power views) and Validation & Customer Support.

• Responsible for Physical Design of a data path design.
• Validation of the MBIST Tool.

• Library characterization tool and methodology development.
• OLA (Open Library Architecture) view generation tool development.
• Layout and Library characterization of 250 nm libraries.