Chiranjeevi panditha

• Verification methodology: UVM.
• Oversaw verification projects at both the top and subsystem levels, using UVM methodology.

TOP‑Level Responsibilities:

• Led the ownership of the Mahua and Bonsai projects at the top level.
• Acted as the primary contact for SKYE and KALPENI Video-IP top-level activities.
• Managed the full top-level verification flow—from testbench bring-up, through netlist, and performance simulations, to final sign-off.
• Qualified the Tensilica Core verification suite and ensured IP compliance across the complete regression suite.
• Performed subsystem checks, including serial-to-parallel block verification, and carried out power-aware simulations, diagnosing and resolving issues.

Block-Level Responsibilities:

• Conducted HF block verification, developed, and brought up the testbench environment.
• Led ownership of the VPP-PPE block, overseeing RTL verification activities.
• Designed randomized testbench setups and stimuli to improve functional and code coverage.
• Developed both white-box and black-box coverage models, authored new UVM test cases, and sequences.
• Built functional coverage groups, and drove coverage closure.
• Leading code coverage reviews with designers to address unreachable and dead code, and maintain waiver lists (FSM, line, branch, etc.).
• I wrote automation scripts, including an unpacker tool, to validate input vectors before running them on the DUT.

• Verification methodology: VMM.
• Led ownership of the PHY-SerDes project, managing the ATE environment.
• Redesigned the entire ATE testbench into a modular architecture (Intel requirement) to support on-the-fly rate changes.
• Enhanced functional and code coverage through comprehensive test development and optimization.
• Developed and debugged SystemVerilog assertions (SVA), raising overall assertion coverage.
• Investigated and resolved clock-checker issues.
• Conducted and debugged daily ATE regressions (TESTCHIP), and managed internal regression runs.

• Point of contact (POC) for the MIPI-SPMI verification project using UVM methodology.
• Designed and implemented master, and slave passive components.
• Developed comprehensive functional and corner-case test sequences, and built the testbench environment for simulations.
• Created functional coverage groups and improved overall coverage metrics.
• Added debug ports to streamline the debugging process.
• Led daily regression and debugging activities.
• Delivered customer-specified enhancements by analyzing user requirements, and designing system architecture and specifications.