Chun Jin Teoh

IP Integration Validator on D2D and Package Validation
Intel 14th Generation & Next Generation Client SoC (2020 - Current)

• Lead validation of Intel FDI (Foveros Die Interconnect) D2D IP integration validation for Intel client SoC projects.
• Develop an overall validation strategy and testbench strategy for Compute Tiles in Intel Die-disaggregation SoC projects.
• Conduct package validation to verify interactions of tiles at the pre-silicon stage, identifying logic design bugs and architecture gaps.
• Actively leading and contributing to the Front-End Methodology Workgroup, focusing on simulation model build strategies, model performance, and test environment strategy.

IP Integration Validator on Fabric Connectivity, PCIE & DMI
Intel 11th Generation Client SoC (2017 - 2019)

• Validated the connectivity of Fabric IP in SoCs, ensuring various IPs could communicate via Intel's in-house protocol.
• Engaged in the integration validation of PCIe and DMI IPs for Intel client SoCs.
• Contributed to the Front-End Methodology Workgroup, focusing on simulation model build strategies and testbench strategies.

IP Integration Validator on Fabric Connectivity
Intel Mobile SoC (2012 - 2016)

• Validated the connectivity of Fabric IPs in SoCs, enabling communication between various IPs using Intel's proprietary protocols.

Micro-architecture Validator on Memory Cluster
Intel 5th Generation Processor (Broadwell) (Date of Employment)

• Validated Data Cache Units and Translation Lookaside Buffers (TLBs) at the micro-architectural level.
• Developed and executed test plans to ensure functional correctness of the IPs.