Cissy Jose
Cherthala
Summary
Dynamic ASIC Front End RTL Design Engineer with 7 years of extensive experience in RTL design, recognized for delivering innovative and efficient solutions. Expertise in developing designs using SystemVerilog, Verilog, and VHDL, complemented by robust knowledge of 5G technology, including the development of MIMO (beamforming) features from the ground up. A dependable team player thriving in fast-paced environments, adept at adapting to changing project demands while maintaining a focus on achieving optimal results. Strong analytical skills and creative problem-solving abilities consistently contribute to project success and drive continuous improvement.
Overview
14
14
years of professional experience
1
1
Certification
Work History
ASIC Front End RTL Design Engineer
Wipro Limited
08.2024 - Current
- Working as ASIC Front end RTL designer
- Developing digital design in System Verilog/Verilog/VHDL codes, based on project requirement.
- Developing and checking the functionality of the blocks in Xcelium.
- Knowledge in IP integration.
- Working in AXI/ECI/APB interfaces.
- Knowledge on Lint/CDC.
- Working on Spyglass/VCSpyglass and running the ERICSSON goals.
- Working on synthesis.
- Hands on experience in GIT, JIRA, Clear Case.
- Hands on experience in CI tools like JENKINS.
- Knowledge in Agile way of working.
- Knowledge in Sprint
- Knowledge in IP processing.
- Knowledge in STA.
RTL Design Engineer(5GFH)
VVDN Technologies
06.2021 - 08.2024
- Worked as RTL designer.
- Developed VHDL coding based on project requirement.
- Developed RTL in VHDL language.
- Developed Architecture of design based on requirement.
- Knowledge on STA.
- Knowledge on Lint.
- Handled RU in 5G project based on 3GPP specifications.
- Developed beamforming based on 3GPP specifications.
- Developed FHIP based on 3GPP specifications.
- Testing RU with end-to-end equipment.
- Handled eCPRI, ORAN, Beamforming (MIMO).
- Knowledge in GIT and JIRA
- Debugging real time issues.
- Took classes (project explanation and doubt clarification) to customers.
Project Intern
DRDO
07.2019 - 04.2020
- Assisted senior Scientists in a real time project.
- Developed Verilog code for Ethernet Synchronization for a real time project.
- Worked on FSM modeling using VHDL /Verilog HDL.
- Worked on RTL Simulation and Synthesis.
Teaching Faculty
Time
08.2015 - 02.2016
- Successfully handled high school students as a Mathematics teacher.
- Forge relationships with parents and also higher authority and develop a sense of loyalty and trust.
- Organized and maintained planning reports and assessment documents of students.
VLSI and Embedded Engineer
Focuz Infotech
10.2013 - 01.2015
- Developed program in VHDL and Verilog HDL for display of a hospital.
- Good hands on RTL coding using VHDL /Verilog HDL.
- Worked on FSM modeling using VHDL /Verilog HDL.
- Worked on RTL Simulation and Synthesis.
- Worked on Programming FPGA Boards using Chip Scope-Pro.
- Imparted trainings to assistants on the Digital Design concepts, products and software.
- Assisted seniors in programming in Embedded C to deliver timely products.
Production Engineer (Electronics)
MDE
01.2012 - 02.2013
- Assisted senior engineers to troubleshoot and determine technical problems.
- Assisted Design Department to make necessary developments in products.
- Handled the tasks of assisting senior engineers in designing and developing R& D laboratory.
- Responsible for modifying and developing new electronic tools and equipment.
- Imparted training to technicians on the use of equipment.
- Handled the major tasks of testing the circuits and features of medical equipment.
- Ensure that the Work Products meet the customer required standards.
- Provided the support to the production team preparing the Work Documents.
- Provided the support to planning team in Work plan.
Education
M.tech - VLSI and Embedded Systems
MANGALAM college of Engineering
Kottayam01.2020
PG Diploma - VLSI and Embedded Hardware
NIELIT
Calicut07.2013
B.Tech - Electronics and Communication
LMCST
Trivandrum, Kerala01.2011
HSE - Bio-Maths
NSS HSS
Nedumudy01.2007
SSLC - undefined
BBMHS Vaisyambhagom
Vaisyambhagom01.2005
Skills
- VHDL
- Verilog
- System Verilog
- Spyglass tools
- Cadence Xcelium tool
- Xilinx Vivado
- ISE
- ASIC/FPGA Design Flow
- Digital Design Methodologies
- RTL Coding
- FSM based design
- Digital design
- Simulation
- Synthesis
- Static Timing Analysis
- LINT
- CDC
- TCL scripting
- Xilinx Zynq-Ultrascale 67DR
- Linux
- Windows Family
- ERICSSON’s IP processing
- UPF
- Jenkin
- Beamforming
- MIMO
- ORAN Spec
- GIT
- JIRA
- C
Certification
PG Diploma in VLSI and Embedded Systems from NIELIT Calicut
Languages
English
Advanced (C1)
Malayalam
Advanced (C1)
Hindi
Advanced (C1)
Projects Handled
- ECP_X and CPRI_ECP_X modules
Client : ERICSSON
Duration : 2024-10-01 - Present
Doing Spyglass checks based on ericsson goals(Lint/CDC) and synthesis. Updating the modules based on the requirements in SV and VHDL language.Environment is GIT. Doing CI in Jenkin tool. Did the migration from Clear Case to GIT. Leading the design team and working in
agile. Owner of the IP.
- Developed Beamformer (MIMO)
Client : AMLITECH USA
Duration: 2023-06-01 - 2024-08-31,
Developed beam-forming modules based on the customer requirement. Language handled in VHDL and tool is xilinx. Done debugging in
Xcelium as well as in hardware.
- Developed FH-IP in 5G domain
Client : AMLITECH USA, MAVENIR, VVDN(Own FHIP), Eridan, HFCL
Duration: 2021-06-01 - 2024-08-31
Developed ORAN and ECPRI modules based on the customer requirement. Language handled in VHDL and tool is xilinx. Done debugging
in Xcelium as well as in hardware.
- Implementation of an Ethernet based Synchronization scheme for Data Acquisition Networks
Client: DRDO( Indian Navy)
Duration: 2019-07-01 - 2020-03-31
Designed Ethernet based synchronization scheme for data acquisition networks for Underwater Towed Array system. Codes are developed
in Verilog and implemented in Waxwing Spartan 6.
- Scrolling LED Display
Client : Focuz Infotech Productions
Duration : 2013-10-01- 2014-10-01
Designed an LED display in Embedded background integrated with VLSI.
- Design and Synthesis of Differential Pulse Code Modulation CODEC using Verilog
Academic Project
2014-11-01 - 2015-01-31
Developed the Code in Verilog HDL for the transmission of signals. Input signal (in analog form) is encoded at the transmitter end and the
received digital signal is decoded at the receiver end with minimum error.
- Developed Medical Equipment Intelligent Tourniquet
Client: MDE
Duration: 2012-01-01 - 2013-02-28,
Handled the tasks of assisting senior engineers in designing and developing R&D laboratory. Handled the major tasks of testing the circuits
and features of medical equipment.
- Design of 8 bit RISC Processor
Academic Project
Given RISC processor code simulated and made it bug free. Design completed according to the specification given.
- PLC development in CNC systems at HMT Kalamassery
Academic Project
Develops the PLC (Programmable Logic Control) for the working of the CNC (Computerized Numeric Controller) machine.
Personal Information
- Passport Number: W3605456
- ID Type: Passport
- ID Number: W3605456
- Date of Birth: 04/08/1989
- Gender: Female
- Nationality: Indian
- Marital Status: Married
Vlsi Domain Skills
VHDL, Verilog, System Verilog, Spyglass tools, Cadence Xcelium tool, Xilinx Vivado, ISE, ASIC/FPGA Design Flow, Digital Design Methodologies, RTL Coding, FSM based design, Digital design, Simulation, Synthesis, Static Timing Analysis, LINT/CDC, VHDL, Verilog, System Verilog, TCL scripting, Xilinx Vivado/ISE, Cadence Xcelium, GIT, JIRA, JENKIN, Xilinx Zynq-Ultrascale 67DR, Linux, Windows Family
Inter Personal Skills
- Took classes and clarified doubts for Clients on projects.
- Participated in International Conference conducted in Mangalam College of engineering and published the paper.
- Participated in National Conference conducted in Coimbatore and presented paper on DDR4 SRAM.
- Self-driven individual.
- Experienced in electronics designing.
- Strong in communication, presentation and decision-making skills.
- Strong affinity and exposure to cross-cultural work environments.
- Adaptability to new environments.
- Enthusiastic, goal-oriented and ability to work under pressure.
- Possess excellent organizational skills.
- Possess excellent verbal and written communication skills.
Papers Published
FPGA implementation of Dynamic Power Area optimized Reversible ALU for various DSP applications.
Timeline
ASIC Front End RTL Design Engineer
Wipro Limited
08.2024 - Current
RTL Design Engineer(5GFH)
VVDN Technologies
06.2021 - 08.2024
Project Intern
DRDO
07.2019 - 04.2020
Teaching Faculty
Time
08.2015 - 02.2016
VLSI and Embedded Engineer
Focuz Infotech
10.2013 - 01.2015
Production Engineer (Electronics)
MDE
01.2012 - 02.2013
PG Diploma - VLSI and Embedded Hardware
NIELIT
B.Tech - Electronics and Communication
LMCST
HSE - Bio-Maths
NSS HSS
SSLC - undefined
BBMHS Vaisyambhagom
M.tech - VLSI and Embedded Systems
MANGALAM college of Engineering