Dalesh Patle

A detail-oriented Design Verification Engineer with a recently completed M.Tech in Microelectronics from IIT Guwahati. Bringing foundational industry experience in digital verification, a strong command of Verilog/SystemVerilog, and a proven ability to verify complex digital designs through academic projects. Eager to apply my skills in a dynamic environment at Texas Instruments, and contribute to first-pass silicon success.

Wafer space technology|Bengaluru, Karnataka, 

Trainee Design Engineer|July 2025 – present

• Undergoing comprehensive training on industry-standard verification methodologies, advanced SystemVerilog concepts, and UVM
• Gaining exposure to complex SoC architectures and design specifications in preparation for project assignments
• Collaborating with senior engineers and mentors to understand professional workflows and best practices in a corporate environment

• Digital IC Design
• Analog IC Design
• CMOS VLSI Design
• Computer Organization & Architecture (COA)
• System on Chip (SOC) Design
• Semiconductor Device Modelling

Design of a 32-bit RISC processor using Verilog| 2024

• Designed and implemented a 32-bit RISC processor, focusing on a simplified instruction set for high performance and scalability
• Developed and simulated Verilog modules for key processor components, including the ALU, register file, and control unit
• Verified the processor's functionality by writing and running test cases to ensure the correct execution of instructions
• Technologies used: Verilog, Xilinx Vivado

Verilog-based FSM traffic signal controller| 2024

• Implemented a finite state machine (FSM) in Verilog to create a functional traffic signal controller
• Designed the logic to handle standard traffic sequences, timing, and state transitions
• Simulated the design to verify its logical correctness and timing accuracy, ensuring it met all specified requirements
• Technologies used: Verilog, Xilinx Vivado

• Unit Coordinator, National Service Scheme (NSS) Cell, IIT Guwahati | 2024 – 2025
• Teaching Assistant (Semiconductor Device Modelling, Microelectronics Lab), IIT Guwahati