DANIEL PHILIP MOSES PILLI

Roles & Responsibilities:

• Currently handling IO Layouts and responsible for IO modules such as bi-directional pads(IO data and READ Pad)
• As metals were constrained from M0-M4, using these limited metals routing of Data-in and Data-out paths were matched.
• Using totem verified the power drop in IO modules and improved accordingly.
• Matching the power for all the 8 bit IO pads was challenging due to the placement constraints.
• Along with IO modules owned analog modules such as Leakage Detector and RC measurement circuits.
• Pool-Cap, Buffer, Dummy device placement.
• Density,Latch-up, Antenna fixes
• Actively involved in the full-chip verification tasks.
• Responsible for ESD sign off check-list.
• Worked on multiple revision history for the projects.

SCRIPTS

• Self learnt Cadence SKILL Script Language.
• Developed few utilities such as Partial Mark Net, Previous Cursor co-ordinates visibility, Resistor Area estimation, etc...
• Enhanced the existing layout quality utilities with the help of CAD team such as double via, floating metal checks, Matching Checks.

Roles & Responsibilities

• Supported for Analog and mixed signal modules such as PISO, SIPO, DRIVERS.
• Supported in ECO's and verification checks such as DRC & LVS clean-up.
• Improved routing to match the resistance for 192bits in data path module.
• Involved in power improvement activities.
• Actively involved in full chip verification tasks.