DEEPASHREE B N
SoC Logic Design Engineer | Formal Verification Engineer
Summary
8 years of experience in Formal Verification with master's degree in VLSI Design and Embedded Systems. Proficiency in FV Methodology: creating test plans, building FV testbenches, code assertions and constraints, FV models, apply abstraction techniques to deliver high quality design on schedule. Experience in Verification of SOCs and IPs such as NFC Reader, Reader Tag, PCRM, DDR standards (DDR3, DDR4, DDR5), GPU AI designs, PCIe Gen6.
Overview
8
8
years of professional experience
6
6
years of post-secondary education
Work History
SoC Logic Design Engineer
Intel Technology India Pvt. Ltd.
12.2023 - Current
- Verified the Conflict Queue and Flit Error Injection blocks in the PCIe transaction layer using FPV.
- Verification of timing fixes, area optimization, and performance fixes in PCIe using SEC.
- Using hardware architecture design and RTL implementation details, I defined the FV scope, deployed the right strategy with comprehensive FV test plans to prove correctness while deploying advanced formal techniques, and created abstraction techniques to converge on complex designs to deliver a high-quality design on schedule and articulate the ROI.
- Increased drop quality through FV, revealing 90+ bugs using FPV and SEC.
Senior Silicon Design Engineer
AMD India Private Limited
09.2022 - 12.2023
- Led end to end Formal verification of GPU Designs
- Built robust FV TB environment from scratch for all apps
- Deployed right strategies and verified GPU SoC design for design features, connectivity, Register Verification, implementation versus spec equivalence checking using FV methodology
- Achieved left shift with replacement of various simulation testcases with formal testcases
- Trained peers and junior engineers in Formal Verification
ASIC Digital Design Engineer, Senior I
SYNOPSYS India Private Limited
09.2019 - 09.2022
- Led formal team and Built robust FV infra for 3 DDR Standards. Enhanced and automated Formal flow
- Trained and enabled junior engineer to run FV
- Verified design for connectivity(MTEST, PINMUX and reset values in design) with well over 90K+ assertions in each project using FV CC
- FSM analysis for dead-lock and live locks in design using FV AEP
- Verified sideband collision features using FPV
- Made significant 9-10% increment in toggle coverage from formal verification in overall coverage data
Design Engineer
NXP Semiconductors
08.2017 - 08.2019
- Led a formal team of size 4. Trained junior engineers and interns.
- Developed a robust formal setup for connectivity and FSM analysis: verified deadlock, live-lock, unreachable, single transition, and multi-transition states.
- Verified test bus and PINMUX connectivity in SOC using FV: improved overall coverage by 5%.
- Executed assertion-based verification in the UVM testbench for: PCRM clock-box verification, isolation, and reset value verification.
- Generated scripts to automate formal flow.
INTERN
Mentor Graphics (Siemens)
06.2017 - 07.2017
- Learnt RTL coding and verification using Verilog HDL
- Understood drawbacks of Verilog and implemented constrained random coverage driven verification using SV
- Worked on implementation of Synchronous FIFO.
Education
MTech - VLSI Design and Embedded Systems
M S Ramaiah Institute of Technology
08.2015 - 08.2017
B.E - Electronics and communication
East West Institute of Technology
06.2011 - 07.2015
Skills
Excellent at end-to-end formal verification process execution, from test plan creation through to verification closure
Hands-on experience with Verilog/ System Verilog HDLs, SVA assertions
Languages – System Verilog, Perl, shell, tcl
Tools – VC Formal, JasperGold, Simvision
Accomplishments
- Recognition Award: 09/2024; 03/2025;
- Spontaneous Recognition Award : 05/2021; 08/2021; 05/2022;
- Execution Excellence Award: 05/2021; 12/2021;
- SPOT Award: 12/2020;
- Published a paper “Analog Multipliers for Deep Neural Net Architectures” at 2017 International Conference on Advances in Computing, Communications and informatics (ICACCI'17)
Timeline
SoC Logic Design Engineer
Intel Technology India Pvt. Ltd.
12.2023 - Current
Senior Silicon Design Engineer
AMD India Private Limited
09.2022 - 12.2023
ASIC Digital Design Engineer, Senior I
SYNOPSYS India Private Limited
09.2019 - 09.2022
Design Engineer
NXP Semiconductors
08.2017 - 08.2019
INTERN
Mentor Graphics (Siemens)
06.2017 - 07.2017
MTech - VLSI Design and Embedded Systems
M S Ramaiah Institute of Technology
08.2015 - 08.2017
B.E - Electronics and communication
East West Institute of Technology
06.2011 - 07.2015
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