Summary
Overview
Work History
Education
Skills
Languages
Timeline
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Deepthi Vaddepalli

Hyderabad

Summary

Highly-motivated employee with desire to take on new challenges. Strong worth ethic, adaptability and exceptional interpersonal skills. Adept at working effectively unsupervised and quickly mastering new skills.

Overview

8
8
years of professional experience

Work History

Physical Design Engineer

Intel Corporation
Hyderabad
01.2022 - Current
  • Responsible to execute from RTL22DSII along with corresponding sign-off flows like FEV, VCLP, timing, RV and LV closure for SOC partitions and IPs.
  • Majorly worked on 10nm, Intel3 and Intel3E technologies.
  • Provided technical support to other team members on implementation issues and challenges.
  • FEV expertise support for multiple designs at org level.

Design Automation Engineer

Intel Corporation
Hyderabad
07.2020 - 12.2021
  • Involved in flow and methodology development and bug fixing.
  • Supported multiple projects in fixing multiple FEV issues like RTL parsing issues, Non-eq debug, LP checks, Runtime reduction and resolving aborts, Audit checks etc.
  • Gained expertise in Conformal tool and fixing issues at different levels of the designs from partition level to Full chip level.
  • Developed training materials and conducted training sessions for new team members.
  • Collaborated with cadence on fixing multiple conformal tool bugs and enhancements.

Structural Design Engineer

Tessolve Semiconductor
Bangalore
09.2018 - 06.2020
  • Responsible for synthesis, PnR and signoff closure for SOC partitions including LP designs.
  • Worked on Intel 10nm and Samsung 10nm.
  • Worked on flow development for PnR and FEV using cadence tools for Samsung 10nm.

Physical Design Engineer

SoCtronics Technologies
Hyderabad
01.2017 - 09.2018
  • Responsible for PnR and timing closure for test chips.
  • Worked on 22FDSOI and GF14nm technologies.
  • Gained expertise in floorplan, power plan, congestion and CTS recipe building on macro dominant designs.

Physical Design Trainee

Veda IIT
Hyderabad
07.2016 - 01.2017
  • An industry-oriented training in Physical Design flow in VLSI chip design in association with a consortium of VLSI design houses.
  • Performed and analyzed PnR flow for various designs while building strong fundamentals.
  • Gained expertise in TCL, perl and C-language scripting.

Education

Bachelor of Technology - Electronics And Communication Engineering

JNTUH College of Engineering
Karimnagar, Telangana
01-2016

Skills

  • Hands-on experience with tools:

Synthesis and PnR: Design compiler, Fusion compiler, ICC, ICC2, Cadence SOC Encounter, Innovus

LEC/VCLP: Conformal, formality, VC LP

STA: Primetime, tempus

IR-RV: Redhawk_sc

LV: IC Validator, Calibre DRV

  • Scripting skills: TCL, PERL, Unix Shell and C-language
  • LEC expert

Languages

Telugu
First Language
English
Advanced (C1)
C1
Hindi
Upper Intermediate (B2)
B2

Timeline

Physical Design Engineer

Intel Corporation
01.2022 - Current

Design Automation Engineer

Intel Corporation
07.2020 - 12.2021

Structural Design Engineer

Tessolve Semiconductor
09.2018 - 06.2020

Physical Design Engineer

SoCtronics Technologies
01.2017 - 09.2018

Physical Design Trainee

Veda IIT
07.2016 - 01.2017

Bachelor of Technology - Electronics And Communication Engineering

JNTUH College of Engineering

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Deepthi Vaddepalli