Devang Shah
SoC Design Engineer
Bengaluru,Karnataka , INDIA
Summary
Overall 6 Years of experience as SoC Design Engineer with a demonstrated history of working at Intel Technology India Pvt Ltd which includes 1 year of internship in the same domain . Skilled in RTL2GDS Flow, Clock Tree Synthesis, Logic Synthesis, Static Timing Analysis, Formal Verification, low power checks, power optimization, ASIC flow, PNR , ROM Programming, ECO, UPF, Automation.
Overview
6
6
years of professional experience
8
8
years of post-secondary education
Work History
SoC Design Engineer
Intel Technology India Pvt. Ltd
Bangalore, Karnataka INDIA
06.2017 - Current
- Handled multiple designs Convergence from Synthesis to Layout along with responsibility of converging timing, DRC, power, FEV, Quality(caliber),Low power checks ( VCLP ) . ( ~300k to 2m gate count ) with clock frequency up to 2GHz on 14nm,10nm,7nm,3nm for multiple Xeon Server SoCs.
- Leading team and Successfully delivered 2 subfc consists of 20 partitions for multiple Xeon server SoCs.
- Timing Constraints development/generation, timing constraints validation, signoff Static Timing Analysis and subfc & block-level timing closure for Multiple SoC.
- Responsibility of power optimization techniques implementation to meet power targets for Multiple Server Xeon SoCs.
- Handled automation to generate IO constraints based on RTL clock connectivity which helped Multiple SoCs at initial stage for timing analysis.
- Handled Multiple Functional/Logical/Floorplan ECO in designs which helped to pull tapin by 4 weeks. ( Logical + Functional )
- Experience in implementation & Programming of ROM for SoC.
- Handled Timing/FEV/Cross-talk/Noise/Low power/power Convergence at partition level and Subfc level for Multiple Xeon Server SoCs.
- Handled Noise analysis and fixes at full chip level
- Knowledge on Chip Level Floor planning, Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
- Work closely with RTL designers to debug and root-cause Physical Implementation issues related to design, tools, etc. and arrive at a feasible solution through input and design collateral
- Lead various methodology efforts to reduce execution time and improve quality metrics.
- Successfully completed several tapeouts under fast paced design environment with tough deadlines.
Graduate Intern
Intel Technology India Pvt. Ltd
Bangalore, Karnataka INDIA
06.2016 - 06.2017
- Performed scan insertion in synthesis Timing analysis and fixing setup/hold violations in SoC Partitions.
- Converged multiple small designs WRT timing/power/FEV/Quality.
- Performed Multiple automation with help of scripting (TCL).
Education
M.Tech - Communication
Nirma Institute of Technology
Nirma University - Ahmedabad Gujarat, India 07.2015 - 06.2018
B.E ( Electronics And Communication Engineering ) -
Dr Jivraj Mehta Institute of Technology
Anand-Gujarat, India 07.2010 - 06.2015
Skills
Scripting Language : TCL, PERL(Basics), Shell, Bash
Awards
- DTA ( Division Team Award ) for Coming up with Path breaking solution to deliver critical partition on time.
- Project level Award In recognition of driving SoC channel SD evaluation/definition, structural design of all fabrics and synthesis quality for all partitions.
- Project level Award for Outstanding contribution towards Xeon Server SoC timing closure activities.
Declaration
I hereby declare that all the information stated above is true to the best of my knowledge and belief
Timeline
SoC Design Engineer
Intel Technology India Pvt. Ltd
06.2017 - Current
Graduate Intern
Intel Technology India Pvt. Ltd
06.2016 - 06.2017
M.Tech - Communication
Nirma Institute of Technology
07.2015 - 06.2018
B.E ( Electronics And Communication Engineering ) -
Dr Jivraj Mehta Institute of Technology
07.2010 - 06.2015
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