Devegna P. Kanzariya

A VLSI engineer with experience in RTL Design and problem solving, focused on efficient digital design and optimization. Proficient in FPGA development using Vivado and experienced with Cadence tools including Virtuoso, Genus, and Innovus. Familiar with open-source design flows such as OpenLANE and Yosys. Capable of resolving design challenges, improving workflow efficiency, and collaborating with teams to deliver reliable and high-quality design solutions.

• Part of a finalist team in the National 1-TOPS Semiconductor Program, selected to develop industry-grade RISC-V SoC (Top 37 of 550+ submissions).
• Developed 'Nirmal Jal,' a self-driven solar + wind powered system that purifies salt sea water into distilled water; project grant by SSIP.

• Date of Birth: 10/04/2003
• Gender: Male
• e-mail ID: devegnak@gmail.com
• Contact number: +91 90545 65610

• CSIR-CEERI - Pilani, 10 days hands-on training on IC fabrication from cleaning of the wafer to dicing of the wafer.
• SCL - Chandigarh, Visited SCL to get real-world exposure and aspiration by the fabrication of RISC-V based processor like Vega processors.

• Completed a 10-day intensive fabrication training at CSIR-CEERI Pilani, gaining hands-on experience in cleanroom processes including lithography, oxidation, and etching to fabricate functional semiconductor devices.