Summary
Overview
Work History
Education
Skills
Timeline
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Diganchal Chakraborty

Bengaluru,KA

Summary

I am an innovative R&D Engineer in simulation and verification software within Synopsys with more than 16 years of experience collaborating with cross-functional teams to develop cutting edge software in Electronic Design Automation industry. I am a meticulous designer with patience and dedication to delivery of polished applications and adhere to expressed specifications. I am a dedicated problem solver, establishing systems for technical troubleshooting and design flaw resolution.

Overview

18
18
years of professional experience

Work History

Senior Staff R&D Engineer

Synopsys
06.2012 - Current
  • Research and development of a new hardware generation language capable of providing higher levels of abstraction during hardware construction
  • Architecting Synopsys-Design-Constraint verification software for efficient solution.

  • Enhanced and integrated waveform reconstruction, RTL to GATE name mapping components to HAPS prototyping and specified requirements to improve QoR, usability and functionality for various other Verdi components including netlist elaboration, quick synthesis and waveform viewer.
  • Managed all aspects of the project including requirements, development, validation, customer deployment and customer support.
  • Performed as a tech lead to other developers, trained new resources, reviewed code, assigned issues, held team meetings, wrote and reviewed documentation.
  • Worked closely with product validation team, reviewed test-plans, provided R&D support and commitment, arranged for machine/storage resources, coordinated issues related to data security.
  • Communicated seamlessly with various parties, including Verdi product management, HAPS product teams and management, generated status reports and attended recurring cross-product meetings.

Staff R&D Engineer

Abbvie, Inc
07.2015 - 12.2019
  • Supported RTL to GATE name mapping solution deployment at customer sites and contributed to convergence and stability of the Power Replay product. Worked closely with application engineers to refine use models, and automate different parts of the flow.
  • Architected and Implemented many enhancements and bug fixes that improved functionality, usability and QoR of the name mapping engine.
  • Performed as a tech lead and provided guidance and training to other developers. Supported the improvement efforts in the processing of the register optimization data read by the name mapping engine.

Senior R&D Engineer II

Medtronic Inc.
11.2012 - 07.2015
  • Ported register optimization data from synthesis product into the RTL to GATE name mapping engine. Collaborated with various teams from synthesis, formal verification products to implement a flow that can produce a high mapping rate. Achieved 95%+ mapping rate across several customer designs and this helped setup the Power Replay product, which is still being used in several major customer accounts.
  • Developed GUI for UVM Aware debugging capability, a new enhancement to the Verdi3 Automated Debug System. Designed and implemented data viewers to display UVM configuration, factory, phase and sequence information. This included features such as filtering and cross-probing with other Verdi3 views (source viewer, class/object browser, call stack viewer etc.,)
  • Transaction Debug: Developed C APIs for dumping simulation transaction data into FSDB format, for application in a C modeling environment.

Principal R&D Engineer

Springsoft Inc.
04.2006 - 11.2012
  • Primary R&D for the RTL to GATE name mapping engine. Enhanced and maintained heuristics of the engine to generate mapping between gate-level verification results and RTL design descriptions while retaining the flexibility to take advantage of synthesis tool generated reports.
  • Integrated name mapping engine with combinational waveform reconstruction tool, test bench regeneration for what-if analysis, design source and waveform viewers.
  • Worked on all aspects combinational waveform reconstruction tool. This included various use model flows, performance optimization, logic fanin-cone expansion, fanin-cone value propagation, result display and FSDB dumping.
  • Developed a batch mode capability of the combinational waveform reconstruction engine, including a verification utility which compared the results of the current run with a golden FSDB.

Education

Master of Science - Electrical Engineering

The Ohio State University
Columbus, OH

Skills

  • Software Development, Architecture and Flow Design
  • Technology and Process Integration
  • Project Management
  • Compiler Technology
  • Verilog/VHDL simulation
  • Problem Resolution
  • Low power verification technology
  • Assertion extraction from simulation traces
  • Design constraint verification
  • Python Binding API development for Compilers
  • C API for Simulation Debug
  • Analytical Thinking
  • Logic synthesis
  • IT Skills
  • Code Compliance
  • Verilog / VHDL Modeling and Digital Design
  • Alternative hardware generation language modeling and development
  • MLIR infra-structure and hand on experience
  • C, C, Verilog, Systemverilog, VHDL , TCL, Python, UNIX Shell Scripting

Timeline

Staff R&D Engineer

Abbvie, Inc
07.2015 - 12.2019

Senior R&D Engineer II

Medtronic Inc.
11.2012 - 07.2015

Senior Staff R&D Engineer

Synopsys
06.2012 - Current

Principal R&D Engineer

Springsoft Inc.
04.2006 - 11.2012

Master of Science - Electrical Engineering

The Ohio State University

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Diganchal Chakraborty