Dimpy Hasija
Summary
Results-driven Verification Engineer with 13+ years of experience. Dedicated and adaptable professional with a proactive attitude and the ability to learn quickly. Strong work ethic and effective communication skills. Eager to contribute to a dynamic team and support organizational goals.
Overview
13
13
years of professional experience
Work History
Design Verification Engineering Manager
Intel
Benguluru
07.2019 - Current
- Worked on verification on chipset fabric like UCIE, D2D, and MDFI.
- Directed team members for fabric validation in SoC.
- Directed team and worked on the development of a C-based constraint random portable stimulus generator for SoC Verification.
Lead Verification Engineer
Cerium Systems
- Led subsystem-level verification activity from Verification Plan to Regression Debugs & Monitoring.
Senior Verification Engineer
Wipro Technologies
01.2015 - 05.2018
- Worked on USB 3.1 Link Layer Verification Suite.
- Worked on AHB Interconnect Verification.
Engineer
eInfochips Pvt Ltd
10.2011 - 01.2015
- Worked on block level verification activity, 737 Max Display.
- Worked on test cases development for Nested Interrupt controller.
Research Associate and Assistant Professor
Sharda University
Education
Advance Diploma in VLSI Design -
Sandeepani School of Embedded Systems
M.Tech (Nano Science & Technology) -
Panjab University
B.Tech (Electronics and Communication) -
Maharishi Dayanand University
Skills
- Methodology: OVM, UVM
- HVL: System Verilog
- HDL: Verilog
- Protocols: AXI4, AHB, USB31, UCIE
- Programming Languages: C
- Strategic Planning
- Coaching and Mentoring
- Innovation management
Accomplishments
- Awarded with Inspiring Performance award for minimum turnaround time for the activity.
- Awarded as PES SHINING STARS for quick regression debugs.
- Pat on the Back award for Disciplined execution of Block Verification (737-Max Display).
Publications
- An Effective way of generating constraint random traffic in processor driven SoC Verification, poster presentation at Intel Event
- Opportunities, Challenges and Current Trends in MEMS Industry, Proceedings of International Conference on Sensors and Related Networks (SENNET'09), VIT University, Vellore, India. Dec. 08-10, 2009. pp.379-384
- Design and Simulation of Micro Cantilever based Biosensors, published in Book: Advances in Nanotechnology and Cryogenics pp.29-35
Timeline
Design Verification Engineering Manager
Intel
07.2019 - Current
Senior Verification Engineer
Wipro Technologies
01.2015 - 05.2018
Engineer
eInfochips Pvt Ltd
10.2011 - 01.2015
Lead Verification Engineer
Cerium Systems
Research Associate and Assistant Professor
Sharda University
Advance Diploma in VLSI Design -
Sandeepani School of Embedded Systems
M.Tech (Nano Science & Technology) -
Panjab University
B.Tech (Electronics and Communication) -
Maharishi Dayanand University
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