DINSHITH D

FPGA-Based Verification of ASIC Design - Internal Project.

• Implemented ASIC design into FPGA design (integrating multiple communication protocols connected via an interconnect and controlled by a RISC-V processor) and achieved timing closure, fixing implementation issues by 4 weeks.
• Migrated Vivado-based project to Quartus-based project within a week.
• Converted flash memory from one vendor to the specifications of another vendor. Reduced project completion timeline by 25%.
• Rapid identification of bugs with simulation via VCS and ModelSim, and emulation results via STP, with high accuracy.
• Created detailed FPGA design documentation and a compilation tracking system in Excel, streamlining debug workflows and enabling faster onboarding for new engineers.

Test Card Development for eUSB2V2 - Client: Intel.

• Translated system requirements into microarchitecture; implemented and verified eUSB2v2 protocol on Intel FPGA.
• Authored UVM test cases and debugged via VCS/Verdi, ensuring protocol compliance under most corner cases that can be covered via the available simulation setup.
• Optimized placement and routing to resolve timing violations, boosting throughput by 20%.
• Performed emulation-based debugging for the eUSB2v2 test card, addressing corner cases that cannot be covered by the simulation environment, and ensuring full protocol compliance.
• Delivered eUSB2v2 test card under Intel spec in six months.

Development of Transport Layer Protocol for USB4 - Test Card Client: Intel.

• Contributed up to 35% on micro-architecture development and correction of design.
• Developed a modular SystemVerilog testbench for subsystem-level verification of USB4 TLP, enabling comprehensive coverage, and delivering bug-free functionality.
• Diagnosed and resolved clock domain crossing (CDC) issues in the USB4 TLP subsystem by redesigning FIFO access logics and splitting large blocks into smaller, optimized units, boosting output clock frequency from 220 MHz to 520 MHz, exceeding the 325 MHz target by over 60%.