DIVESH TIWARI
Hyderabad
Summary
Strategic VLSI professional with over 13 years of extensive experience, specializing in the physical implementation and optimization of high-performance integrated layouts. Proven track record at Synopsys and Broadcom leading the layout architecture for advanced FinFET and Gate-All-Around (Gaa) nodes, specifically across 5 nm, 7 nm, and 8 nm technologies.
- Layout Optimization Expert: Highly skilled in driving layout-driven area and power reductions for complex MPRF custom memory macros, focusing on high-density bit cell arrangements, and optimized floor planning for sense amps and control blocks.
- Physical Sign-off & Efficiency: Expert in achieving final sign-off by resolving complex pin access challenges and ensuring strict DRC & DFM compliance to minimize area usage, without compromising reliability for macros.
- Strategic Technical Leadership: Adept at managing project timelines and resource allocation for high-stakes product launches, while fostering a culture of layout innovation and operational excellence.
Overview
13
13
years of professional experience
Work History
Manager M4 AMS Layout Design
Synopsys India Pvt Ltd
Hyderabad
06.2015 - Current
- Designed advanced nodes (FinFET/GaA)-based standard cell layouts for 2 nm, 3 nm, 4 nm, 5 nm, 7 nm, and 8/10/12/16/28/22/55/130 nm technologies, enhancing performance and efficiency.
- Designing special cells, like Multi Bit cells, Synchronizers, Level Shifters, POK Kits, Delay Cells, and End (Physical Only) cells.
- Experience in designing various libraries and memory macros for legacy technologies such as 28 nm, 130 nm, and 55 nm.
- Managed project timelines and resource allocation for product launches.
- Led document management initiatives for the Quality Management System, improving compliance, and process efficiency.
- Executed pin access debugging using advanced tools like ICC2/FC, optimizing final sign-off for a faster application by 10 percent for pin-dense cells.
- Innovated processes aimed at reducing turnaround time, and enhancing automation across projects.
- Tools/Skills: Custom Compiler ICC2, FC, Virtuoso XL, shell scripting, Calibre, IC Manager, and debugging.
IC Design Engineer (Memory layout)
Broadcom Communication Private Ltd
Mumbai
12.2012 - 06.2015
- Executed top-level integration for array and control blocks for top-level design and verification for MPRF custom memory cells, ensuring compliance with LVS/DRC standards, with block-level floor planning, signal and power planning, and reliability different verification checks for TSMC and SMIC.
- Designed MPRF memory macros for read-write configurations, including Bit Cell Design, Sense Amp, Control Blocks, and Leaf Cells, enhancing production quality layouts by incorporating maximum DFM rules and minimizing area usage.
- Completed layout designs for 8 macros, adhering to area and power constraints while optimizing clock-lib buffer integration.
- Performed extensive checks, latch-up and EM/IR analysis across multiple node technologies (130nm NM).
- Collaborated on multiplexed I/O layouts with peripheral blocks, managing clock generation, and pre-decoder modules.
- Tools/Skills: Custom Compiler ICC2, FC, Virtuoso XL, shell scripting, Calibre, IC Manager, debugging.
Education
Mtech - VLSI Design
IITR
RoorkeeVLSI Design
Cdac
TICA Mumbai02-2013
Bachelor of Engineering - Electronics & Communication Engineering
Disha Institute of Management And Technology
Raipur06.2011
Skills
- Design and architecture: standard cell layout (Gaa/FinFET), MPRF memory macro architecture, bit cell and sense amp design, top-level integration
- Physical verification: advanced DFM compliance, DRC/LVS/antenna sign-off, EM/IR analysis, latch-up and reliability verification
- EDA tools and automation: custom compiler, ICC2/FC, Virtuoso XL, Calibre, IC manager, shell scripting for process automation
- Strategic leadership: project management and resource allocation, quality management systems (QMS), operational efficiency optimization, mentoring and team growth
Hobbies and Interests
- Active interest in music
- Nature
- Outdoor activities
- Enjoy mentoring
- Team sports
- Creative pursuits like singing and landscape photography
Languages
Hindi
Native
Native
English
Advanced (C1)
C1
Timeline
Manager M4 AMS Layout Design
Synopsys India Pvt Ltd
06.2015 - Current
IC Design Engineer (Memory layout)
Broadcom Communication Private Ltd
12.2012 - 06.2015
Mtech - VLSI Design
IITR
VLSI Design
Cdac
Bachelor of Engineering - Electronics & Communication Engineering
Disha Institute of Management And Technology