Summary
Work History
Education
Skills
Projects
Declaration
Timeline
Generic
G Rishikesh Rao

G Rishikesh Rao

Kurnool

Summary

An avid learner and passionate VLSI Engineer with two year of industry experience in accord with VLSI industry.Dynamic and results-driven Verification and Emulation Engineer with extensive experience in the development and validation of complex digital designs. Proven expertise in creating and implementing comprehensive verification and emulation strategies to ensure the functionality, performance, and reliability of digital systems.

Work History

Emulation Engineer

wipro
kochi
11.2022 - 05.2023

Client : NXP semiconductors ,austin ,USA.

Projects : CRR respository ,IMX93 .

Common register repository , nirvana 1 soc (12/2022-5/2023)

  • CRR or common register repository is a NXP flow for register informationRegister data in CRR format is authored by H/W designers and is used togenerate documentation, UVM for verification flows, S/W register header files and debugger files so that they are all in sync. Many of these outputs are used by NXP to deliver to customer.
  • Generating header files by using scripts to verify register attributes like reset, write/read. Test case development for attributes like reset, write/read, mask values, size and offset of the registers.
  • All the registers in total of 150 modules are verified and tests developed for all modules Reported bugs to document owners, designers and verification owners.

IMX93 guel soc (5/2021-12/2022)

  • Analyse the scope, define, build and bring-up emulation models, adapt and enhance the debug infrastructure, which includes debug infrastructure development, debug failures and ensure functionality as per specifications
  • Worked on scripting languages like Perl, Tcl, Shell script
  • Worked in Zebu Emulation platform, VEGA and HAL script updating running test case.

Education

RTL Design And Verification Course -

Maven Silicon
Banglore
08-2021

B.Tech -

Rajeev Gandhi Memorial College of Engineering And Technology
09-2020

Intermediate -

Narayana Jr College
03.2016

SSC -

Sri Lakshmi High School
03.2014

Skills

  • HDL: Verilog
  • HVL: SystemVerilog
  • Verification methodologies: Constraint Random Coverage Driven Verification, Assertion Based Verification - SVA
  • TB methodology: UVM
  • Protocols: APB, AHB, AXI, SPI , I2C, UART
  • EDA tool: Questasim

Projects

AMBA AHB2APB Bridge RTL design - 

The project involves designing an RTL model for a bridge that connects the AHB  and APB buses.

The purpose of the bridge is to facilitate communication between components or peripherals connected to the AHB and APB buses.

I2C  Protocol - Implemented the I2C (Inter-Integrated Circuit) communication protocol for smart sensor node capable of collecting data from various sensors, enabling seamless data exchange between master and slave devices.

SPI  Protocol-Implemented the Serial Peripheral Interface (SPI) protocol for smart sensor node capable of collecting data from various sensors, establishing a communication framework for data exchange between a master device and multiple slave devices .

UART Protocol - Implemented the Universal Asynchronous Receiver-Transmitter (UART) protocol for a sensor, enabling serial communication between devices with asynchronous data transmission with multiple baud rates.

Drowsiness detection using facial feature emotions.

The main objective of the project is to design a security or alerting system that prevents accidents that occurs due to the drowsiness of the driver. This system recognize the drowsiness of the driver based on the facial expression of the driver and alerts the driver using MATLAB simulink R2019 .

Router 1x3 - RTL design and Verification, Architected the block level structure for the design. Implemented RTL using Verilog HDL. Architected the class based verification environment using System Verilog. Verified the RTL model

using Verilog, System Verilog, UVM, Qestasim and ISE .

Declaration

I hereby declare that all the information contained in this resume are true to my knowledge. I take full authority for the correctness of the written information.

Timeline

Emulation Engineer

wipro
11.2022 - 05.2023

RTL Design And Verification Course -

Maven Silicon

B.Tech -

Rajeev Gandhi Memorial College of Engineering And Technology

Intermediate -

Narayana Jr College

SSC -

Sri Lakshmi High School
G Rishikesh Rao