Durga Prasad Podagatla
Bangalore
Summary
7years and 6months of hands on experience in SoC Design Verification (DV) and Formal Verification (FV). Extensive expertise in SOC DV flow and good knowledge on Jasper Gold Apps FPV, Connectivity. Proven ability to lead SoC verification projects end-to-end, including specification reviews, verification plan (vPlan) creation, Testbench bringup, regression management, and silicon debug. Successfully contributed to the development of more than 10 SoCs for Automotive and general-purpose MCU applications. Worked as Verification lead for 3 projects. Strong track record of driving multiple design verification projects with effective team leadership and cross functional collaboration from project inception through to silicon debugs and customer support.
Overview
7
7
years of professional experience
Work History
Design Verification Manager
Texas Instruments
Bangalore, Karnataka
08.2024 - Current
- Company Overview: https://www.ti.com/
- Lead and mentor a team of six engineers, assigning goals and providing real-time feedback.
- Collaborate with architects, RTL, PD, and firmware teams for requirement analysis and effort estimation.
- Plan and coordinate verification tasks for new projects, including testbench bringup.
- Drive weekly DV meetings to track progress, communicate project updates, and resolve conflicts.
- Review specifications and customer requirements; participate in verification reviews and silicon debug as needed.
Design Verification Lead
Texas Instruments
02.2023 - 08.2024
- Led verification for TI MSP M0 Microcontrollers across three projects, managing end-to-end DV from planning to silicon debug and customer issue resolution.
Core team member for MSP SoC Power, Clock, and Reset modules. - Directed development and implementation of Power-Aware RTL, Gate-Level, and AMS simulations; managed regressions for every RTL release.
- Established SoC DV environment, executed sanity tests, identified and collaborated on RTL issues with RTL team.
- Led Gate Level Simulation bringup, analyzed SDF warnings, and guided juniors in debugging GLS issues.
- Ensured quality by analyzing simulation warnings, reviewing code of junior engineers, and providing constructive feedback
Senior Design Verification Engineer
Texas Instruments
06.2021 - 02.2023
- Verified complex multi-clock, multi-power domain Mixed-Signal IP "System Controller" using Jasper Gold Formal Property Verification.
- Developed auxiliary blocks and reference models to support complex formal assertions.
- Contributed to PMCU block SoC Design Verification using SystemVerilog alongside IP DV team.
- Developed and deployed an innovative SoC Connectivity Verification Flow, reducing bug detection time and finding 10x more connectivity issues than traditional methods.
Design Verification Engineer
NXP Semicondutores
Noida, Uttar Pradesh
01.2020 - 06.2021
- Company Overview: https://www.nxp.com/
- Verification of On-Chip NVM Memory (Flash) at the System-on-Chip (SOC) Level.
- Design and management of System-on-Chip (SoC) Testbench, including Boot, Code, and Data placements through scatter files.
- Creation of VCDs for Power Analysis of the SoC, both in the Run and Standby domains, to implement test cases for generating high traffic on the SOC to determine the maximum power dissipation.
- Https://www.nxp.com/
Design Verification Engineer
Sevya Multimedia
Noida, Uttar Pradesh
05.2018 - 01.2020
- Company Overview: https://www.sevyamultimedia.com/
- Verification of the robustness of the Clock and Reset Architecture at the System-on-Chip (SOC) level using the Intelligent Hardware Stress Generator (IHSG) Methodology.
- Implementation of assertion-based verification to ensure the stability of asynchronous signals input to the synchroniser.
- Https://www.sevyamultimedia.com/
Internship
Sevya Multimedia
Noida, Uttar Pradesh
- Company Overview: https://www.sevyamultimedia.com/
- Developed an asynchronous FIFO design utilising Grey Pointers, and generated conditions for fifo_empty and fifo_full.
- Verified the asynchronous FIFO design using System Verilog.
- Https://www.sevyamultimedia.com/
Education
B.Tech - Electronics and Communication Engineering
Rajiv Gandhi University of Knowledge Technologies
05.2018
Pre University Course - undefined
Rajiv Gandhi University of Knowledge Technologies
04.2014
Skills
- SOC Verification
- Clock, Reset and Low power Design
- Formal Verification
- Verification lead
- UVM
Personal Information
Title: Design Verification Engineer
Timeline
Design Verification Manager
Texas Instruments
08.2024 - Current
Design Verification Lead
Texas Instruments
02.2023 - 08.2024
Senior Design Verification Engineer
Texas Instruments
06.2021 - 02.2023
Design Verification Engineer
NXP Semicondutores
01.2020 - 06.2021
Design Verification Engineer
Sevya Multimedia
05.2018 - 01.2020
B.Tech - Electronics and Communication Engineering
Rajiv Gandhi University of Knowledge Technologies
Pre University Course - undefined
Rajiv Gandhi University of Knowledge Technologies
Internship
Sevya Multimedia
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