Pramod B

1) STA Lead for CMN Timing Closure ( Coherent Mesh Network, 3nm, 8/16 Partitions, 2/4 Macros, 1.6GHz, 5 DVFS, ~50M instances):

• Building Understanding of novel CMN architecture and share the understanding to the team.
• Co With SoC STA team in understanding the Signoff corners required for CMN.
• Critical corner pruning related to CMN Flat and CMN block level STA.
• Setup and maintain both Top and Block level STA environments.
• Working closely with Front End Engineers for ontime and correct SDC maturity.
• Run STA and provide constant Feedback to APR teams on every stage of Design Implementation to address placement, clock skew and latency issues early in the design cycle.
• Closely work with DFT teams in understanding and fixing the Scan mode timing paths.
• Planning of block level and top level Pre-TECO cycles before SPO to achieve required SPO.
• Co Work with Top PD team and ensure clock latency targets are achieved for better Interface timing closure.
• Setting up and Maintain Hyperscale STA environment for Macro timing closure and provide high quality HS timing models to top STA teams.
• Planning of TECO Cycles by aligning with APR and SoC STA team and ensuring timing converges at each TECO Cycles.
• Worked on CMN FLat and Block level STA to address critical internal and interface timing/DRV/Glitch violations.
• CMN interface timing closure at 1.6GHz frequency was challenging, use of innovative solutions such as out of lane buffering in order to reduce SI impact, Data Path restructuring ,IO logic optimization during APR using additional constraints.
• Clock ECOs solutions for hard to fix paths after careful Risk evaluation using PT-DMSA.
• Closely worked with APR team to ensure on tie release of SPEF. delivering TECO TCL and action items to meet the project schedule.
• Trained and mentored junior engineers, providing guidance and direction.

2) DFT Insertions during synthesis, DFT QA and Pattern Generation for CMN Partitions:

3) Static Timing Analysis for 4G and 5G LTE Modem Blocks of a Smartphone SOC at Advanced Technology Nodes:

• Owned LTE 4G/5G modem full flat Pre and Post layout STA execution.
• Correlation checks between full flat modem pre-STA and block synthesis timing.
• Working closely with FE integrators for SDC maturity on time.
• Understanding of full Signoff corners and developing MCMM STA run targets.
• Co-work with PD block owners and ensure SPEF annotation quality is achieved.
• Scan mode timing analysis and co-work with the DFT team to come up with suitable timing-related fixes.
• Provide placement-related, skew-related feedbacks to PD at each P&R stage.
• Provide TECO TCL files using Tweaker to PD and make sure that timing fixes will cause minimal impact on Congestion, Shorts, DRC, etc.
• Analyze Signal level violations, SI, and Glitch analysis and co-work with PD block owners to find solutions for fixing the same with minimal impact.
• Running STA by using top context from SoC and ensuring good correlation between Modem ad SoC timing.

4) Partition Level Advanced Physical Aware Synthesis and Design Integration of 4G/5G LTE mode Blocks, Image Signal Processing blocks, Infra Subsystem of Contemporary Smart Phones SoC at Advanced Technology Nodes:

• Performing Top/Block Level Advanced Physical Aware Synthesis using Design Compiler, exploring various synthesis recipes and optimization techniques to achieve set PPA targets.
• Co-Working with top-level ATPG teams and come up with scan plan and perform DFT Insertion.
• Co-work with the Floor planning team and come up with physical constraints (DEF) and perform physical aware advanced synthesis.
• Co-working with P&R team in memory placement and deciding core area utilization ratio.
• Co-working with Physical implementation to solve congestion, Timing, and converge on Area constraints.

5) Partition Level Netlist QC Checks (ERC/LEC/TETRAMAX/CLP/PTPX/PRESTA)

• Performing ERC checks at Top/Block level.
• Logical Equivalence check of Top/Block to functional intent of the Design is preserved.
• Fixing all DFT DRC violations and Obtaining coverage numbers and delivering ATPG patterns to the TOP level DFT team using TetraMax.
• Working closely with Design Verification team to obtain RTL/gate-level simulated FSDB’s for various low power scenarios, setup and run PTPX and report and analyze power numbers
• Generate UPF and Perform Conformal low power checks and ensure the power intent of the design is preserved.