G Jahnavi

VLSI graduate with expertise in RTL design, digital design, and computer architecture. Demonstrated proficiency in Verilog HDL, RISC-V processor design, and FPGA implementation. Experienced in ASIC RTL-to-GDSII flow utilizing Cadence Genus and Innovus, with a solid understanding of synthesis, placement & routing, and STA basics. Skilled in verification through Verilog testbenches and waveform debugging, alongside proficiency in Linux and EDA tools.

ALU and Bit-Manipulation Unit, designed a 32-bit ALU with arithmetic, logical, shift, and bit-manipulation ops (BEXT, BDEP, REV); simulation verified UART and SPI protocols, implemented UART and SPI modules with baud-rate generation in Verilog; verified via simulation and FPGA testing Traffic light controller (FSM) designed a Verilog FSM-based 4-way traffic controller with timing counters, simulation verified Smart Glasses & Stick, Developed sensor-based assistive device for real-time obstacle detection and user alerts. ASIC RTL-to-GDSII Flow, Performed synthesis, P&R, CTS, and basic STA for a 32-bit RISC core using Cadence Genus & Innovus.

• Verilog HDL
• SystemVerilog (basic)
• C (basic)
• Python (basic)