Garima Singh
Lucknow
Summary
To work in a challenging environment demanding all my skills and efforts to explore and adapt myself in different fields and realize my potential where I get the opportunity for continuous learning.
Overview
14
14
years of professional experience
7
7
years of post-secondary education
3
3
Languages
Work History
DFT Trainee
VLSIGURU Training Institute
04.2024 - Current
- Expertise in complete DFT flow including Scan insertion, Compression, ATGP and Simulations
Teacher
National Thermal Power Corporation Ltd.
05.2022 - 06.2022
- Company Overview: GEM (CSR) Project
- GEM (CSR) Project
Assistant Professor
Bansal Institute of Research and Technology
12.2015 - 11.2016
- Teaching subjects at undergraduate level
- Marking and taking lab sessions and tutorials
- Supervising undergraduate level students in the department for final year projects
Assistant Professor
Babulal Tarabai Institute of Research and Technology
01.2015 - 08.2015
- Organized training and workshops at departmental level to enhance technical skills and awareness for research in students
Assistant Professor
DIT University
08.2013 - 01.2015
Guest Faculty
Institute of Engineering & Technology
01.2011 - 01.2012
Education
B.tech - EC
Amity University
Lucknow 01.2005 - 04.2009
M.tech - VLSI Design
Banasthali University
Rajasthan 01.2010 - 04.2012
Skills
Design For Testability
Technical Papers
- Subodh Wariya, Garima Singh, Vishant, R.K. Nagaria, S. Tiwari, Design Analysis of XOR(4T) Based Low Voltage CMOS Full Adder Circuit, IEEE, International Conference on Current Trend in Technology (Nuicone'11), Ahmedabad, India, pp. 1-7, 2011
- Adarsh Kumar Singh, Neeraj Kumar Dangwal, Mohan Singh, Manoranjan Kumar, Garima Singh, Anand Singh, Design and FPGA implementation of sequential digital 7-tap FIR filter using microprogrammed controller, International Journal of Scientific & Engineering Research, pp. 1391-1394, 5, 4, April, 2014
Personal Information
- Date of Birth: 07/01/87
- Gender: Female
- Nationality: Indian
Projects Details
Institute of Engineering & Technology (I.E.T), Dr. Subodh Wariya, Performance Analysis of Xor/Xnor Based CMOS Circuits for low voltage VLSI applications., The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage., The objective of this work is to investigate the trade-off that is possible at the circuit level in order to reduce power dissipation while maintaining the overall system throughput. The reduction of the power dissipation and the improvement of the speed required optimization at all levels of the design procedure.
Disclaimer
I hereby declare that the above-mentioned particulars are true to the best of my knowledge and belief.
Timeline
DFT Trainee
VLSIGURU Training Institute
04.2024 - Current
Teacher
National Thermal Power Corporation Ltd.
05.2022 - 06.2022
Assistant Professor
Bansal Institute of Research and Technology
12.2015 - 11.2016
Assistant Professor
Babulal Tarabai Institute of Research and Technology
01.2015 - 08.2015
Assistant Professor
DIT University
08.2013 - 01.2015
Guest Faculty
Institute of Engineering & Technology
01.2011 - 01.2012
M.tech - VLSI Design
Banasthali University
01.2010 - 04.2012
B.tech - EC
Amity University
01.2005 - 04.2009
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