GAURAV PRATAP GARG
Pratap Nagar, Jaipur
Overview
5
5
years of professional experience
Work History
DFT Engineer
Texas Instruments Pvt Ltd
Bangalore
08.2022 - Current
- Verified the completeness and correctness of test controls in RTL design.
- Worked on PMT TDL generation for analog modules.
- Performed connectivity checks on DFT RTL for early RTL issue detection.
- Implemented scan insertion and DRC cleanup for SoC.
- Handled stuck-at and TDF pattern generation; achieved 98% coverage.
- Developed internally generated scan-enable sequences.
- Closed ATPG and connectivity issues; supported pattern sign-off.
- Built the vManager regression flow to reduce regression run effort.
- Worked on programmable BIST, block-level scan insertion, and pattern generation for SA, TDF, and SoC lint.
Application Engineer
Interra Systems Pvt Ltd
Noida
08.2021 - 08.2022
- Worked on Memory Description Language (MDL), Memory Compiler tool (MC2), Template Expansion Language and GDSViewer tool to ensure cleanliness in development of MC2 tools’ features as per the customer’s requirement.
- Developed automated flow to make the CCBs out of the spice netlist using Python and Interra’s SOM-tool.
- Maintained Touchstone automated flows for memory characterization.
- Improved regression testcase coverage of MC2 and Touchstone tools using GCov Tool.
DFT Intern
STMicroelectronics Pvt Ltd
Greater Noida
02.2020 - 06.2020
- Understood DFT Flows and Insertion Methodologies.
- Worked on Gate Level Simulations for TFT Faults.
Education
Bachelor of Engineering - Electrical & Electronics Engineering
Birla Institute of Technology Mesra
RanchiHSC - PCM
Sony Academy Senior Secondary School
Bharatpur Rajasthan SSC -
Bhagat Singh Modern Secondary School
Bharatpur, Rajasthan Skills
- HDL: Verilog
- OS : Linux, Windows
Scripting
- Python
- CShell
Tools
- Cadence Genus
- Cadence Modus
- Simvision
- vManager
- Jasper Gold
Languages
- Hindi
- English
Hobbies and Interests
- Indian History
- Playing Cricket
- Listening Hindi & Punjabi Music
Academic Projects
- Data (Audio, Image, etc.) Transfer using Light Fidelity.
- Design and Fabrication of DC Voltage Booster using PWM Feedback.
- Investigation and Analysis of Active Power Factor Correction Techniques.
https://www.linkedin.com/in/gaurav-pratap-garg
Timeline
DFT Engineer
Texas Instruments Pvt Ltd
08.2022 - Current
Application Engineer
Interra Systems Pvt Ltd
08.2021 - 08.2022
DFT Intern
STMicroelectronics Pvt Ltd
02.2020 - 06.2020
Bachelor of Engineering - Electrical & Electronics Engineering
Birla Institute of Technology Mesra
HSC - PCM
Sony Academy Senior Secondary School
SSC -
Bhagat Singh Modern Secondary School
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