Summary
Work History
Education
Skills
Professional Training
Academic Honor
Working Roles & Responsibility Experience
Projects
Tool Exposure
Personal Information
Disclaimer
Timeline
Generic
Gautam Kumar

Gautam Kumar

Patna

Summary

Seeking a respectful position in Core Multinational Company where I can effectively contribute my skills as a professional, possessing technical skills for the advancement and growth of the organization and thus leading to my career growth.

Work History

IP Hardware validation engineer

PSG, INTEL CORP
  • About 1 year 8 months

Internship

PSG, INTEL CORP
  • About 1 year

Education

M.Tech - VLSI Design & Embedded

Indian Institute of Technology (IIT) Patna
Patna
06-2022

B. Tech - Electronics And Communication Engineering

Silicon Institute of Technology, BPUT
Bhubaneshwar
10-2019

12th Standard - PCM

The Earth Public School, C.B.S.E
Patna
04-2014

10th Standard -

A.V.N English School, C.B.S.E
Patna
03-2012

Skills

  • Hardware Validation experience on 25G, 50G, 100G, 200G, 400G Ethernet IPs
  • Experience with External Ethernet testers, Spirent N11U - FX3, DX3
  • Good debugging skills using Quartus Signal Tap Probe Analyzer, System Console toolkits
  • Good scripting experience with Python,TCL
  • Good experience on Intel regression suite for automation
  • Good documentation skills on IP Hardware validation test plan creation, Coverage plan creation for IP HW Val sign-off
  • Strong understanding on FPGA Design flow and unit level simulation

Professional Training

  • Done training on Python and TCL basics.
  • Done training on FPGA and Verilog.

Academic Honor

  • Qualified GATE -2019,2020
  • Secured Rank 1 in exam for Selection of Students for VLSI Project in B.Tech.

Working Roles & Responsibility Experience

  • Currently working on Ethernet IP Hardware validation and Reg suite automation
  • Intel Regression suite-based test automation enhancement using Python/TCL
  • Writing hardware test scripts in TCL for test enhancement
  • External tester-based Ethernet IP qualification for IP Performance, Bandwidth, throughput and MAC feature qualifications
  • Generate IP HW test reports and Analyze for failures
  • Responsible for raising tickets to different stakeholders based on analysis
  • Active RTL debug using STP tool to corner the issue
  • Responsible to create comprehensive Test Plan and coverage plan for Ethernet IP
  • Run IP Example design simulation to qualify every release for screening basic sanity issues
  • Out of Box testing and fully script automated RegSuite testing for over 200+ Ethernet IP Configurations for every Quarter release cycle

Projects

  • Worked for the VLSI project named 'Low Power SPI accessible SRAM' using Cadence virtuoso tool.
  • Attended Boot camp on VLSI in e-COE, Bhubaneswar in December 2018.
  • Verilog implementation of the SPI controller Completed a summer training course about electronics and telecommunication at BSNL.

Tool Exposure

  • Intel Quartus Tool
  • Cadence Virtuoso & Layout Editor
  • Mentor Graphics
  • Modelsim

Personal Information

  • Passport Number: S6338048
  • Father's Name: Uday Kumar
  • Mother's Name: Meena Devi
  • Date of Birth: 01/11/96
  • Languages: English, Hindi

Disclaimer

I hereby declare that the information furnished above is true to the best of my knowledge and subject to verification.

Timeline

IP Hardware validation engineer

PSG, INTEL CORP

Internship

PSG, INTEL CORP

M.Tech - VLSI Design & Embedded

Indian Institute of Technology (IIT) Patna

B. Tech - Electronics And Communication Engineering

Silicon Institute of Technology, BPUT

12th Standard - PCM

The Earth Public School, C.B.S.E

10th Standard -

A.V.N English School, C.B.S.E
Gautam Kumar