Girish Kunamneni

Physical Design course include

• ASIC & FPGA Design Methodologies
• HDL: Verilog
• Physical Synthesis
• Floor-Planning and Placement
• Clock Tree Synthesis (CTS)
• Routing
• Static Timing Analysis (STA)
• Physical Verification (DRC and LVS)
• Tcl Scripting
• Perl and Python Scripting

• My responsibilities include support design, buy-off, installation and validation of automated production lines
• Process Characterisation / Optimisation (DFMEA's, PFMEA's DOE's etc.)
• Lead systematic technical root cause investigations
• Support production line ramp to achieve mature production targets
• Develop and implement production/processing methods and controls to meet quality standards in the most efficient manner for new and existing additive manufacturing processes.

• Worked as a Digital Design Engineer in RnD department of Baseband (MODEM) and FEC teams for Radio communication system development projects
• Developing RTL modules for MODEM/FEC related algorithms as per the given specification
• Worked on Data encoding techniques and Digital Signal Processing algorithms for Clock & Data recovery, phase detection & correction, data demodulation processes and their implementations
• RTL design using VHDL/Verilog
• Worked on different Xilinx FPGAs
• Hands on experience with EDA tools like XILINX ISE, VIVADO, PlanAhead
• Hands on experience with Matlab and Simulink tools
• RTL design debug using chipscope, HDL verifier, and FPGA-in-loop simulation, FPGA data Capture
• Designed Butterworth filters for Baseband (IQ) filtering using NI multisim and ADS tools
• Implemented in hardware and tested
• Experience in Simulations, Synthesis, STA and CDC Analysis, hardware debug
• Worked on different digital modulation techniques, FEC algorithms and MODEM development.

• Technology Node / Layers: 128nm / 10 Metal Layers
• Tools: cadence Innovus
• Clocks / Frequency: 1 / 2.02 GHz
• Instance Count / Macros: 8k / 4
• It is an ALU block(practice block)
• FloorPlan, Powerplan, Placement, CTS, Detail Routing.