Gothresh Madapati

Project: RTL and Netlist Power Analysis Automation (3 nm, CPU, and Mesh IPs)

• Developed an automated flow from RTL simulation to netlist power analysis, boosting efficiency by 20%.
• Created a Streamlit dashboard to track power trends, cutting manual effort by 30%.
• Enhanced clock gating and Q-to-CP ratio, with real workload FSDB data, reducing power by 10–12%.
• Designed test scenarios for idle and worst-case conditions, improving power accuracy by 10%.

Project: Centralized RTL Power Flow (5 nm, CPU, and Mesh IPs)

• Built a centralized, Python-based RTL power analysis flow, automating reports for multiple IPs.
• Lowered non-gated cell count by 15% in idle modes, with custom efficiency reports.
• Partnered with design teams to optimize power, achieving a 10% efficiency gain.

Project: Initial RTL Power Analysis (7nm, PCIe IP)

• Performed an initial power analysis using existing tools, identifying early inefficiencies.
• Analyzed power reports, reducing leakage by 5% with actionable recommendations.

Project: AXI and PCIe Data Path Verification

• Verified AXI and PCIe traffic paths in a 7 nm SoC, attaining 100% functional coverage with SystemVerilog/UVM.
• Resolved verification failures using Verdi, working closely with the design and firmware teams.
• Conducted SoC-level GLS verification for power-aware and non-power-aware netlists, addressing X-propagation and voltage issues.
• Guided junior engineers and refined GLS flows with Tcl scripts, decreasing debug time by 15%.