Summary
Overview
Work History
Education
Skills
Internship
Timeline
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GOURAB PAUL

SENIOR RTL DESIGN ENGINEER, QUALCOMM
Bengaluru,KA

Summary

A proficient RTL Design Engineer having 4.5+ years of experience in multiple ASIC design domains ,with proven track record of working in high performing ASIC Front End Design Team focused in developing QUALCOMM's custom AI Subsystem .

Overview

5
5
years of professional experience

Work History

RTL Design & Integration

QUALCOMM
02.2022 - Current
  • Worked on the RTL Coding using SystemVerilog-HDL for Qualcomm's custom AI Compute Subsystem.
  • Responsible for RTL checks clean-up like VCS, Lint, CDC,PLDRC ,etc.
  • Responsible for UPF design and tool clean-ups for design compliance for Lint, CDC and CLP violations for the owned block having multiple power domains.
  • Worked closely with multiple stakeholders - Verification, MBIST and DFT - for timely delivery of the subsystem RTL.
  • Worked on power measurement analysis of the chip using PrimeTime PX by Synopsys and measured various power consumed for a high performance testcase.
  • Supported & guided various cross functional teams like Software, Synthesis, Validation and Soc throughout the project lifecycle.
  • Successfully delivered 5 projects tapeout under high-pressure, stringent timelines.

Design Verification Engineer

QUALCOMM
04.2020 - 01.2022
  • Hands on experience with UVM ,System Verilog based testbench.
  • Hands on experience on Verdi & Dve tool by synopsys for debugging the test failures.
  • Formal verification using connectivity checks.
  • RAL based verification for config registers.
  • Knowledge of APB,AHB, AXI protocols.
  • Developing and porting dedicated C test for feature based verification.
  • Brought up Low Power verification environment for compute AI subsystem involving UPFs.
  • Power Aware GLS verification closure for power critical design.
  • System Verilog based assertions(SVA) for feature based verification.
  • Performed both Code as well as functional Coverage closure for all the projects involved into.
  • Successfully delivered 3 projects tapeout under high-pressure, stringent timelines.

Systems Architecture & C Modelling

QUALCOMM
07.2019 - 01.2020
  • Involved in C modelling of a Image Compression IP, which can compress various raw image formats like NV12, TP10 , Bayer,etc.
  • Analysis of different custom Image compression algorithms for lossy/lossless compression .
  • Did comparative analysis of the existing compression algorithm vs proposed one using python to code both the models and filed IDF for the same.

Education

M.E - EMBEDDED SYSTEMS

BITS PILANI
GOA
04.2001 -

B.TECH - ELECTRONICS AND COMMUNICATION ENGINEERING

FIEM
KOLKATA
04.2001 -

HIGHER SECONDARY - 88.4%

KALYANI PUBLIC SCHOOL
KOLKATA
04.2001 -

SECONDARY - 80%

THE CENTRAL MODERN SCHOOL
KOLKATA
04.2001 -

Skills

  • Language: Verilog, System Verilog, C,C, Python, UVM,OOPS

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    Internship

    QUALCOMM-(Jan-2019 - June-2020)

    • Worked on comparative analysis of SiFive's RISC-V microcontroller vs ARM cortex M3 for power management IP engine in terms of PPA.

    Timeline

    RTL Design & Integration

    QUALCOMM
    02.2022 - Current

    Design Verification Engineer

    QUALCOMM
    04.2020 - 01.2022

    Systems Architecture & C Modelling

    QUALCOMM
    07.2019 - 01.2020

    M.E - EMBEDDED SYSTEMS

    BITS PILANI
    04.2001 -

    B.TECH - ELECTRONICS AND COMMUNICATION ENGINEERING

    FIEM
    04.2001 -

    HIGHER SECONDARY - 88.4%

    KALYANI PUBLIC SCHOOL
    04.2001 -

    SECONDARY - 80%

    THE CENTRAL MODERN SCHOOL
    04.2001 -

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