Summary
Overview
Work History
Education
Skills
Achievements
Timeline
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Grishma Shah

Grishma Shah

ASIC Design Verification Engineer
Nadiad

Summary

10+ years of experience as an ASIC Design Verification Engineer in SOC verification, IP verification, FPGA verification, VIP development.

I am committed for ensuring the quality and reliability of designs, I aim to utilize my expertise in verification to deliver efficient and robust verification solutions.

Overview

13
13
years of professional experience

Work History

Senior Verification Engineer- Level 1

Einfochips
04.2012 - 11.2014
  • Defining verification plan and Verification Environment development utilizing System Verilog and UVM (Universal Verification Methodology skills
  • Developing and debugging test cases, managing and updating regression scripts, coding functional coverage and assertions and achieving 100% explicable functional coverage
  • Developed scripts to automate repetitive tasks, saving countless hours of manual effort across projects.
  • Verification of MIPI CSI-2 and MIPI DSI IP
  • Verification of MIPI UFS Host Controller IP

Design Verification Engineer

Einfochips
05.2008 - 03.2012
  • Defining verification plan and Verification Environment development utilizing System Verilog and UVM (Universal Verification Methodology skills
  • Developing and debugging test cases, managing and updating regression scripts, coding functional coverage and assertions and achieving 100% explicable functional coverage
  • Development of VIP for MIPI – CSI2, MIPI CCI
  • Migrated MIPI-CSI2 OVM VIP to VMM methodology
  • Verification of Weighted Random Early Detection (WRED) RTL
  • Verification of two FPGAs that are part networking field. Worked on block level as well as system level verification of FPGA - Verification of Router block and FIFO block of FPGA.


Engineer Trainee

Einfochips
12.2007 - 05.2008
  • During my training program, I got opportunity to work on Multilayer AMBA AHBLITE Verification IP Development

Senior Verification Engineer Level 2

Einfochips
04.2017 - 03.2019
  • SOC verification
  • Defining verification plan and Verification Environment development utilizing System Verilog and UVM (Universal Verification Methodology skills)
  • Developing and debugging test cases, managing and updating regression scripts, coding functional coverage and assertions and achieving 100% explicable functional coverage
  • Mentored junior engineers to help them grow professionally and contribute effectively to the team's success.
  • Verification of Motion sensing SOC – TAP Detection block and FIFO Block.
  • Responsible for System level verification of the blocks as well as block level verification og the blocks
  • Responsible for GLS ( Gate Level Simulation)

Member of Technical Staff - Level 1

Einfochips
04.2019 - 10.2020
  • Responsible for complete verification closure of 3 blocks of the motion sensing chip and those blocks are TAP Detection block and FIFO Block and Power Sequencer Block
  • Defining verification plan and Verification Environment development utilizing System Verilog and UVM (Universal Verification Methodology skills)
  • Developing and debugging test cases, managing and updating regression scripts, coding functional coverage and assertions and achieving 100% explicable functional coverage
  • Mentored junior engineers to help them grow professionally and contribute effectively to the team's success.
  • Responsible for System level verification of the blocks as well as block level verification og the blocks

Education

Bachelor of Technology - Electronics And Communications

Dharmsinh Desai University
Nadiad, India
04.2001 -

Skills

  • Verification Methodologies : UVM, VMM OVM

  • Protocols: MIPI Based protocols CSI-2, DSI, UFS HCI, CCI

  • Protocols: I2C, SPI, AMBA AHB, WRED algorithm

  • Coverage Driven Verification

  • Scripting Languages: Makefile, Perl

  • Programming Languages : C, C, Python

  • Others: Coverage Driven Verification, System Verilog Assertions, GLS

Achievements

  • Awarded with "Caught in the Act Award" in 2009 for MIPI CSI Verification IP development.
  • Awarded with "Pat on the Back Award" in 2012 for MIPI CSI, MIPI DSI IP verification.
  • My efforts were appreciated by awarding "Embrace Impossible Challenge" in 2018.
  • Awarded "Best Project Award" in 2019

Timeline

Member of Technical Staff - Level 1

Einfochips
04.2019 - 10.2020

Senior Verification Engineer Level 2

Einfochips
04.2017 - 03.2019

Senior Verification Engineer- Level 1

Einfochips
04.2012 - 11.2014

Design Verification Engineer

Einfochips
05.2008 - 03.2012

Engineer Trainee

Einfochips
12.2007 - 05.2008

Bachelor of Technology - Electronics And Communications

Dharmsinh Desai University
04.2001 -

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Grishma ShahASIC Design Verification Engineer