GURUPADAYYA SHIDAGANTI
Bengaluru
Summary
Mixed-signal circuit design engineer with over nine years of experience in developing high-quality designs. Expertise in I/O standards including DDR and LVCMOS, along with multiple mixed-signal IPs. Proven ability to meet stringent performance requirements, and deliver projects on time.
Overview
9
9
years of professional experience
Work History
Principal Design Engineer
Cadence Design Systems
Bengaluru
08.2025 - Current
- Presently working on the IO cell architectures in advance nodes using core devices
Staff Design Engineer
Arm
Bengaluru
04.2024 - 08.2025
- Led the development of the time to digital converter IP which is part of delay monitor and droop detector sensors in arm cpu's.
- Collaborated with cross-functional teams, including RTL, implementation, and DFT, to improve performance and testability.
- Contributed to new sensor validation methodologies for multiple EDA views, enhancing overall validation processes.
Senior Design Engineer
Arm
Bengaluru
03.2021 - 04.2024
- Designed and validated overdrive IO circuits, power cells, and power management cells using advanced FDSOI and FinFET technologies
- Developed reference generation circuits and oscillator cells to optimize circuit performance and reliability
- Contributed to a patented tolerant combo RX circuit, enhancing features for overvoltage, failsafe and tolerant operations
- Managed the complete IO library development process, ensuring high-quality outputs from specification to release
Design Engineer
Arm
Bangalore
04.2019 - 03.2021
- Responsible for designing and validating critical IO circuits and libraries, ensuring high reliability and performance standards
- Developed General Purpose IO circuits and fail-safe IO libraries in advanced nodes, enhancing product robustness
- Validated overdrive IO libraries through rigorous EMIR and other reliability checks, ensuring compliance with industry standards
- Generated and validated FE EDA views, contributing to the overall efficiency of the design process at Arm
Design Engineer
Sankalp Semiconductor
Hubli Area
07.2016 - 04.2019
- Designed and verified basic analog building blocks including current mirrors, OPAMPs, single stage, differential amplifiers and IO building blocks for DDR, LVDS and LVCMOS IO standards
- Developed TX and RX circuits and other sub blocks compliant with DDR, LPDDR and LVCMOS IO standards during training
- Contributed to the design and verification of DDR combo supporting DDR3, DDR4, and LPDDR4 in FDSOI technology
- Worked on Verilog modeling of PLL
Education
Bachelor of Engineering -
B. V. Bhoomaraddi College of Engg. & Tech
Hubli05.2016
Skills
- Exposure to high-speed RX and TX architectures for DDR3 and DDR4 (Worked on combo DDR receiver which will support both DDR3 and DDR4)
- Have a good understanding of equalization techniques, like CTLE, DFE
- Well-versed in mismatch mitigation techniques, like auto-zeroing in the RX front end
- Well versed in high-speed LS architectures
- Have a good understanding of high-speed I/O signaling topologies
- Led the development of a time-to-digital converter IP, which is part of delay monitor and droop detector sensors, which can support a maximum clock frequency of 45 GHz in advance nodes
- Interacted with SOC architects, physical design engineers, RTL engineers, and DFT engineers while developing mixed-signal IPs, such as delay monitor and droop detector
- well-versed with basic analog building blocks like current mirrors, single-ended, and differential amplifiers ,OPamp's and BGR and voltage reference circuits used in over drive IO libraries
- Total 3 US patents approved
Tools
- Virtuoso Schematic Editor
- Virtuoso ADE
- Spectre
- Tessent
- Liberate
Timeline
Principal Design Engineer
Cadence Design Systems
08.2025 - Current
Staff Design Engineer
Arm
04.2024 - 08.2025
Senior Design Engineer
Arm
03.2021 - 04.2024
Design Engineer
Arm
04.2019 - 03.2021
Design Engineer
Sankalp Semiconductor
07.2016 - 04.2019
Bachelor of Engineering -
B. V. Bhoomaraddi College of Engg. & Tech