HANEEFA FATHIMA

Profile Summary:

Skilled physical design engineer with over 5.6 years of experience in complete backend flow. Hands on experience in place & route , ECO flow and familiar with TCL scripting. Looking for a challenging career as a physical design engineer. Self-driven, committed to work with determination and sincerity. Organized and dependable candidate successful at managing multiple priorities with a positive attitude. Willingness to take on added responsibilities to meet team goals.

PROJECT 7:

Team size: 18

Tools used: ICC2, PrimeTime, Formality and Calibre

Technology : N5 (TSMC)

Description: Handled 1 partition of 500k instance count ,

Macro count: 6, which were used in core cpu and operates at frequency

of 3.75GHz

Client: AMD HYD

Role:

• ECO implementation of partition and make it timing/PV/IR/EM clean
• Tran fixes and timing were critical as the channel was very narrow
• Drawing manual routes in higher layers to fix timing and tran violaions in the channel
• SI effect was bad, fixing for si nets was a challenge
• Shorts and drcs were critical ,efficiently worked on physical verification closure

PROJECT 6:

Team size: 26

Tools used: ICC2, PrimeTime, Formality and Calibre

Technology : N6 (TSMC)

Description: Handled 1 partitions 1.5M and 800k instance count respectively, Macro count: 3, which are used in server applications and operates at frequency of 2.17 GHz

Client: AMD HYD

Role:

• To Perform PNR and ECO implementation for both partitions and make it timing/PV/IR/EM clean
• Partition was timing critical and congestion critical worked on getting a good placement database w.r.to routablity with reasonal DRC's and smooth ECO convergence
• Creating bounds for the interface flops to meet interface and internal timing
• Closing timing in one corner was very difficult, enabled optimization for that corner from place and at every optimization stage
• After taking FCT ecos one area become very sensitive w.r.to drc’s, worked on drc fixes (especially shorts) without any delay in meeting deadlines

PROJECT 5:

Team size: 26

Tools used: ICC2, PrimeTime, Formality and Calibre

Technology : N6 (TSMC)

Description: Handled 2 partitions of 1.6M and 500k instance count respectively, Macro count:1, which are used in server applications and operates at frequency of 2.17GHz

Client: AMD HYD Role:

• To perform PNR and ECO implementation for 2 partitions
• Partiton was critical w.r.to congestion and routability, applied density screens ,cell padding and applied hard blockages at the notch area
• Few set of ports were custom routed as those were critical w.r.to interface
• Fixing DRC’s and IR issues was a challenge, as IR violating cell count was high grossly downsized cells which have margin through them, de-clustering these IR reported cells and then applied extra VDD and VSS tapping for left out cells in next iterations
• Fixing FCDRC was critical manually changed routing for those violations

PROJECT 4: Team size: 18 Tools used: ICC2, PrimeTime, Formality and Calibre

Technology : GF 14nm Description: Handled 2 partitions of 1.2M and 500k instance count respectively, Macro count: 1 which are used in server applications and operates at frequency of 2.17GHz

Client: AMD HYD Role:

• Responsible for IO ports placement, floorplannig, PnR flow and Eco implementation
• This block is critical in FCT closure and DRC critical
• Applied partial blockages, path groups and macro modelling to fix drc’s and timing
• Fixed timing violations through RDL routing
• Fixed Dynamic IR issues by spreading the cells and adding decaps, EM fixes with drawing NDR on the nets having violations.
• Diligently absorbed last minute func ecos with minimal iterations and closed the partition in time

PROJECT 3:

Team size: 18

Tools used: ICC2, PrimeTime, Formality and Calibre

Technology : GF 14nm Description: Handled 2 partitions of 1M and 500k instance count respectively,

Macro count: 1 which are used in server applications and operates at frequency of 1.78 GHz

Client: AMD HYD

Role:

• To perform Eco implementation for 2 partitions and worked on timing/IR/PV closure of both blocks
• To write internal ecos , FCT ecos from fullchip reports and to implement them
• Cleaning up shorts and drc’s was the main challenge
• Fixing interface drv’s without causing impact on other paths

PROJECT 2:

Team size: 18

Tools used: ICC2, PrimeTime, Formality and Calibre

Technology : GF 14nm Description: Handled 2 partitions of 1M and 500k instance count respectively,

Macro count: 1 which are used in server applications and operates at frequency of 1.78 GHz

Client: AMD HYD

Role:

• To perform Eco implementation for 2 partitions and worked on timing/IR/PV closure of both blocks
• To write internal ecos , FCT ecos from fullchip reports and to implement them
• Fixing interface drv’s without causing impact on other paths
• Particular area was IR critical area after hold fixes , declustered the cells and down sized the cells which has timing margins in that area

PROJECT 1:

Team size: 6

Tools used: Innovus, Tempus and calibre Technology : TSMC 28nm Description: Handled 1 partition of 1.2M instance count , Macro count – 200 , operating at a frequency of 516MHz

Client: GIGACOM Role:

• To perform PNR, eco implementation and signoff timing/ IR/LEC/PV closure of the block
• Floorplanning was the major task , to have a best floorplan w.r.to IR/routability .
• writing timing manual ecos from FCT reports and giving it to other partitions