Sriharsha Enjapuri

Working on SRAM compliers

• Interact with PnR Implementation teams to understand SRAM challenges faced by them & identify opportunities for overall system level optimization
• Interact with SRAM designers to finalize SRAM architecture for CPU's & GPU's based on the priority of Performance, Dynamic power, Leakage power, Area
• Leading a team of designers working on multiple designs in N3E/N2P which are SinglePort HighDensity Compilers & Custom Latch Array's & UHD Two Port SRAM
• Presented at UDT- VLSID-2024 on topic " A 3nm 4GHz SRAM with improved DFT Scheme to improve at-speed fault coverage"
• Patent applied for "3nm Logic Bitcell based GPU SRAM"

• Lead Designer for N5 based Single Port High Density compilers with features like Write assist,Column redundancy, Read Assist, Power Gating, Dynamic Self-Time, internal scan-chains, High Speed and Low leakage variants. These SRAM are used as L2/L3 caches in Mediatek CPU
• Published paper in VLSID-2022 with Title " A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications"
• Won 2nd Best Paper Award in Mediatek Internal Conference (MTBTECHCON-2020)

• Complete Ownership of 7nm High Speed B256M2(3Ghz) compiler
• SNUG Publication : PTPX + SPICE based SRAM Pin Power Verification

• Verilog modelling of SRAM & Standard cells