Harshitha Reddy Junoothula
Hyderabad
Summary
Experienced professional with a strong DRAM background. Proficient in DDR5 and LPDDR5 architecture design and verification. Committed to continuous learning and staying current with industry trends to contribute to organizational success.
Overview
5
5
years of professional experience
Work History
Senior DRAM Design Engineer
Micron Technology
Hyderabad
11.2022 - Current
- [Y63N] Proposed LPDDR5 design architecture for 32Gb product with minimal changes from legacy design that will reduce the layout and verification effort. Implemented the x4 read operation in LPDDR5 design, which supports only x8/x16 mode.
- [Y62E] Built the STA setup and developed constraints for command shifters block in DDR5 design
- [Y6CA] Deep dive understanding of the read data and command path. Contributed to enhancing the performance of TSV mux placement in 3DS architecture.
- [Z00N] Led the design edit for 91F reticle revision and collaborated with verification and layout teams
- [Y52Q] Ownership of ODT and DVFSC circuit edits and timing checks on read datapath
DRAM Design Engineer
Micron Technology
03.2022 - 11.2022
- Contributed to the generation of TAV netlist, as well as conducting simulations and debugging of TAV patterns
DRAM Verification Engineer
Micron Technology
06.2019 - 02.2022
- Took lead in supporting Y4CA and Y52K TV verification after receiving training from CPVE TV team. Ownership of running and debugging QED flow.
- Supported 9B3A HBM3 logic die TAV verification. Performed regression simulations and debugging, promptly communicating any failures to DE.
- Supported Y52C RNX and One Hot Mux assertion check verification. Subsequently, it was put on hold
- Supported Z41C TAV Tapeout regression BaseDBR verification Developed the CS monitor as part of internal monitor verification Worked on AOCV flow debug where the +/- 3 sigma variation is applied to the TAV SDF
- Supported Z32D 91D TAV verification. Conducted analysis on failed Tapeout regressions with RNX enabled
Education
M.Tech - Communication And Signal Processing, CGPA: 8.75
Indian Institute of Technology, Madras
Chennai05-2019
B.Tech - Electronics And Communications Engineering
IIITD&M, Kancheepuram
Chennai05-2017
Skills
- DRAM design
- DDR5, LPDDR5 architecture
- Digital Design
- Design Verification
- STA
- Cadence Virtuoso
- Spice simulator
- Verilog
Languages
Telugu
First Language
English
Advanced (C1)
C1
Hindi
Upper Intermediate (B2)
B2
Timeline
Senior DRAM Design Engineer
Micron Technology
11.2022 - Current
DRAM Design Engineer
Micron Technology
03.2022 - 11.2022
DRAM Verification Engineer
Micron Technology
06.2019 - 02.2022
M.Tech - Communication And Signal Processing, CGPA: 8.75
Indian Institute of Technology, Madras
B.Tech - Electronics And Communications Engineering
IIITD&M, Kancheepuram