Hemanth MV
Bengaluru
Summary
- Multi-Level Verification: Pre-silicon verification across Core, Cluster, Tile, and SoC levels, ensuring on-time milestone delivery.
- DFx/DFT Specialization: Expert in verifying MBIST (SMS/LARR), and Repair/Redundancy logic for silicon testability.
- PCIe Validation: Validated high-speed link integrity through Near-End and Far-End Loopback and eFuse feature testing.
- Infrastructure Development: Built robust SV/UVM testbenches, including scoreboards, assertions, and functional coverage models.
- Debug Automation: Developed Perl/Database tools for automated PASS/FAIL reporting and early debug hint generation.
- Technical Leadership: Owned end-to-end verification flows while collaborating with RTL/DFT/FW teams and mentoring contractors.
- Quality Focused: Proven track record of managing complex regressions to achieve silicon-ready quality standard
Overview
7
7
years of professional experience
1
1
Certification
Work History
Lead Engineer
Signoff Semiconductor
Bangalore
01.2026 - Current
- Led the end-to-end verification of 7 high-priority AMD DFTDV features, managing the full lifecycle from initial specification to final sign-off while coordinating delivery across a junior engineering team.
- Developed and validated Smart MBIST features and ICL extensions to enhance functionality and performance.
- Managed project timelines and allocated resources to ensure timely product development and delivery.
Sr DFT-DV Engineer
AMD
Bangalore
04.2024 - 12.2025
- Implemented and verified Smart MBIST diagnostic flows, enabling automated failure data logging and bitmap generation for rapid root-cause analysis of memory defects.
- ICL Extraction for Tessent flow which reads the post SSN instruction RTL and builds an ICL model that describes how all TDRs and scan instruments are connected for Tile level and SA2 level.
- Owned end-to-end tile-level SMS verification, coordinating contractors and cross-functional teams for quality execution and timely project delivery.
- Analyzed MBIST failure logs to identify RTL bugs in memory wrapper logic.
- Collaborated with DFT, RTL, and firmware teams to triage issues, review design updates, and ensure DFx logic is ready for silicon bring-up, facilitating smooth transition to production.
- Successfully delivered tile-level verification milestones on schedule, driving closure of functional, coverage, and quality goals.
- Verified SMN register access, address decoding across multiple IPs and SoC tiles, including JTAG to SMN and AXI to SMN control.
- Drove toggle coverage bring-up and closure for DFx logic across XCD chipsets, analyzing coverage reports and resolving gaps via sequencing fixes, constraints and RTL updates.
- Developed Perl-based automation to extract PASS/FAIL results from MBIST and LARR simulations and publish them into databases for tracking.
Design and Verification Engineer
Cadence & Rambus
03.2022 - 04.2024
- Verified PCIe Near-End Loopback (NELB) and Far-End Loopback (FELB) mechanisms to validate TX/Rx data path integrity, lane connectivity and series functionality.
- Verified eFuse to PCIe logic mapping, confirming proper propagation of fuse values explaining lane enablement and speed capability.
- Verified eFuse programming, read and lock mechanisms used for PCIe feature configuration and security enablement.
- Validated loopbacks enable/disable controls via configuration registers and eFuse settings, ensuring correct sequencing and persistence across resets to maintain system reliability.
- Developed functional coverage for PCIe NELB/FELB loopback and eFuse-controlled features, encompassing modes, speeds, lanes, and negative scenarios to enhance testing comprehensiveness.
- Defined randomized sequence for test case execution.
- Wrote system Verilog Assertions for eFuse and loopback features, covering the behavior, control sequencing and Datapath integrity.
- Test case completes the definition of randomized sequence.
Digital Design Engineer II
Intel
06.2019 - 03.2022
- Developed automation frameworks to provide early debug insights for core CPU verification at core level, significantly reducing root-cause analysis time.
- Implemented intelligent log parsing and debugging hint generation to quickly identify failing units, transactions, and scenarios during core-level regressions.
- Developed architecture-level coverage for validating feature completeness and ensuring compliance with architectural specifications.
- Managed core-level regression tool versioning, driving timely upgrades to new releases while maintaining regression stability and debug efficiency.
- Managed core-level regression tool versioning and executed timely upgrades to new releases, ensuring regression stability and effective debug processes.
- Owned end-to-end core-level regression, overseeing setup, execution, monitoring, failure triage, and closure to uphold verification quality.
- Designed and implemented randomized and semi-randomized testcases at the cluster level to stress functional interactions, corner cases, and integration scenarios across multiple blocks.
- Used the Venus tool to bucketize regression failures, identify common failure patterns, and accelerate root-cause analysis.
Education
MBA -
IIM Visakhapatnam
Visakhapatnam 05.2026 - 05.2026
Master of Engineering - VLSI Design
MIT Manipal
UdupiSkills
- Verification Languages: System Verilog, Specman/e, & C
- Methodologies: UVM & SVA
- Simulation Tools: Synopsis VCS, Verdi, Venus, Virtuoso
- Scripting Languages: Perl, Python, Shell & TCL Scripting
- Protocols: PCIe, AXI, UART, JTAG, USB & RS232
Certification
Maven Silicon Certified Advanced VLSI Design and Verification Course, 10/2017 - 04/2018
Timeline
MBA -
IIM Visakhapatnam
05.2026 - 05.2026
Lead Engineer
Signoff Semiconductor
01.2026 - Current
Sr DFT-DV Engineer
AMD
04.2024 - 12.2025
Design and Verification Engineer
Cadence & Rambus
03.2022 - 04.2024
Digital Design Engineer II
Intel
06.2019 - 03.2022
Master of Engineering - VLSI Design
MIT Manipal