HimaBindu Chitrapu

• Contributed to the Development and testing of Soft Error Mitigation, MIPI CSI2, Axi Quad Spi, SmartConnect, XPM CDC, AXI IP's, applying practical knowledge to address feature requirements and hardware Validation Used ILA,VIO, JTAG, UART to perform detailed hardware debugging.
• Coordinated the update of the product guides to reflect the new features and improvements ensuring clear and accurate technical documentation inclined to the release.
• Utilized JIRA for efficient ticket filing,integrated with Jenkins, Confluence, and Perforce ensuring efficient handling of Design and software changes and successful release deployment.
• Led the Failure Analysis and Validation of FPGA and SoC designs effectively addressing the IP , Synthesis , Implementation or Vivado flow issues if any for approximately 2.5K test cases on daily across 360+ IPs with Quality assurance.
• Guided and mentored team (2 -8) members , on understanding the Vivado Flow failures and fostering skill development and contributing to team productivity and Vivado release success.
• Collaborated closely with Program Managers, and cross functional teams to understand the impact on Vivado release and to make sure that has taken consideration in Failure analysis and facilitate engineering solutions and drive successful Vivado release for latest device additions.
• Developed Strong relationships with the simulator vendors (Modelsim, Xcelium, Riviera, Questa & VCS) by communicating issue identified in the conducted pre-qualification simulator testing for third-party simulators along with the Vivado Simulator and get the fix or patch ASAP

Design and Implement Parallel Sensor Interface for generating 12bit gray scale date and camera control interface for MIPI Alliance Standard Camera serial interface CSI2.

• Designed and developed Hsync and Vsync signals to ensure accurate timing and synchronization for high quality image capture
• Implemented I2c and SPI protocols to facilitate efficient senor communication and data transfer, enhancing over all system functionality.
• Managed the DDR3 memory wrappers to support High speed data storage and retrieval handling the high data throughput of the Sensor.
• Developed a system for capturing motion images,ensuring high accuracy and realtime performance.
• utilized ILA, Oscillocopes,VIO for hardware debugging and issue resolution.
• conducted CDC and lint checks and power analysis and STA checks to validate the design integrity and ensure complaince with Timing and power constraints.
• worked closely with other team members and program managers to align on the project goals, share technical insights, and achieve successful integration and performance outcomes.
• created design document and also updated product guide to include feature additions, limitations in that version.

• Interacting with Front end and Back End teams to understand the architecture and design applications.
• As a guest faculty handled the “Fundamentals of FPGA Design” at Anjuman Engineering College,Bhatkal
• As a Technical Consultant handled the “Digital Design using Verilog” workshop at SVPCET,Puttoor, and Andhra Pradesh
• Handled 5 days “VLSI Frontend workshop" for the faculty of CAPE Engineering College. This faculty development program covers the following topics Verilog, System Design, DFT, Verification, Simulation and synthesis issues, Static timing analysis.
• Taught the following subjects for PG Students, faculty people in UTL Technologies Ltd., Bangalore.Subjects Handled: VLSI Design and Verification, Synthesis by Synopsys DC compiler, Testing and Verification of VLSI Circuits.
• As a trainer handled the several projects for B.Tech and M.Tech students and helped them to solve simulation and synthesis issues.
• As a project coordinator handled 10 teams and helped them in front end design and helped them to understand the verification flow.
• Designed and verified the PCIE, I2C ,AHB blocks using Cadence NCsim and Questasim