Hudhaifah Ibn Saleem

Sr. Silicon Design Engineer ( DFT )

Advanced Micro Devices

07.2021 - Current

Designed and deployed static DFT rule checks (clock/reset/data connectivity) for high-complexity SoCs using SpyGlass DFT, reducing ECO iterations for multiple GPU projects.
Owned block-level INT/EXT ATPG pattern generation, coverage closure, and debug, achieving over 99% targeted SoC coverage under strict test time constraints for graphics SoCs.
Developed and delivered advanced fault-model ATPG patterns (cell-aware, transition, n-detect, timing-aware, defect-oriented), ensuring first-pass delivery and meeting ATE test budgets.
Led SoC-level pattern retargeting, simulations, emulations, and pre/post-silicon support, enabling smooth pattern hand-off to PEO
Owned Extest pattern delivery and verification across multiple SoCs; collaborated cross-functionally with back-end, verification, and silicon teams for seamless production deployment.
Drove test-cycle reduction initiatives in Extest mode, publishing multiple internal best practices that resulted in ~10–25% reduction in test time across different product releases.
Piloted the company’s first SSN (Scan Streaming Network) pattern project, achieving 100% first-time-right delivery for the handled test modes
Defined SoC-level DFT/ATPG test strategy, coordinating with RTL, STA, PnR, silicon, and PEO teams to align coverage, timing, and pattern delivery.
Mentored interns and new hires on ATPG workflows, SpyGlass checks, and pattern debugging.
Delivered multiple internal papers and technical posters on Secure DFT Architecture , test-time optimization, and advanced fault modeling inside AMD.
Contributed to scan insertion implementation and sign-off reviews (partial ownership), assisting RTL/DFT integration teams for multi-IP SoCs.
Good scripting foundation using Perl and TCL for ATPG automation, coverage analytics, SSN pattern tuning, and regression flows. Also pursuing research in AI-driven test automation.