
To secure a challenging position in the field of VLSI Design where I can effectively contribute my skills and grow professionally while contributing to the development of innovative and secure chip-level solutions.
Area of Interest : Design For Testability & RTL Design
HDL Languages: Verilog
Design Tools: Cadence (Virtuoso, Innovus, Genus), Xilinx Vivado 20183
FPGA Boards: Basys3, Zybo Z7-10