IKRAN HASHI MAHAMED
VLSI DESIGN AND EMBEDDED SYSTEMS
Faridabad
Summary
Dynamic VLSI Design and Embedded Systems Intern at Manav Rachna Innovation and Incubation Center, adept in SystemVerilog and FPGA design. Proven ability to enhance design quality through effective communication and problem resolution. Contributed to successful verification tests, ensuring compliance with industry standards while fostering teamwork in cross-functional environments.
Overview
1
1
years of professional experience
5
5
Certifications
3
3
Languages
Work History
VLSI Design and Embedded Systems Intern
Manav Rachna Innovation and Incubation Center
01.2025 - Current
- Cultivated direct experience with FPGA (Intel Quartus) and STM32 Nucleo board.
- Ensured functional correctness by verifying RTL designs using Verilog and SystemVerilog with VCS and Verdi.
- Simulated and designed digital and analog circuits using HSPICE; analyzed results in WaveViewer.
- Applied established methodologies in digital verification to achieve reliable outcomes.
- Facilitated communication among cross-functional teams to clarify design specifications.
- Contributed to quality assurance by assisting in debugging design issues through analysis.
- Executed verification tests on VLSI circuits to meet industry standards and minimize errors.
Networks Intern
Ethio Telecom
10.2022 - 12.2022
- Acquired expertise in telecom hardware and signal transmission fundamentals.
- Assisted with diagnostics and protocol analysis to identify issues.
- Collaborated with senior engineers to troubleshoot network problems, enhancing service efficiency.
- Supported implementation of network upgrades, optimizing capacity and boosting data transmission rates.
- Developed foundational understanding of network protocols and tools for future skill advancements.
Education
Master of Technology - Electronics And Communication Engineering
Manav Rachna International Institute of Research And Studies
Faridabad, IndiaSkills
Hardware description languages: SystemVerilog, Verilog, UVM, SVA
Certification
Internship in VLSI Design & Verification: Manav Rachna Innovation and Incubation Center (Jan 2025 – Present)
Accomplishments
Showcased ScanKart AI QR at Startup Mahakumbh 2025, engaging with dignitaries, international delegates, and industry leaders.
PUBLICATIONS
Adaptive Techniques in VLSI: Design and Analysis of Modified Carry Look-Ahead Adder – Hinweis Journal, 2025
Timeline
VLSI Design and Embedded Systems Intern
Manav Rachna Innovation and Incubation Center
01.2025 - Current
Networks Intern
Ethio Telecom
10.2022 - 12.2022
Master of Technology - Electronics And Communication Engineering
Manav Rachna International Institute of Research And Studies