
Dynamic VLSI Design and Embedded Systems Intern at Manav Rachna Innovation and Incubation Center, adept in SystemVerilog and FPGA design. Proven ability to enhance design quality through effective communication and problem resolution. Contributed to successful verification tests, ensuring compliance with industry standards while fostering teamwork in cross-functional environments.
Hardware description languages: SystemVerilog, Verilog, UVM, SVA
Electronic design automation tools: Synopsys VCS, Verdi, HSPICE, ModelSim, Xilinx Vivado, Intel Quartus
Programming and scripting: Embedded C (STM32, Arduino), Python, shell scripting
PCB design expertise: Altium Designer
Interpersonal skills: Fast learning, teamwork, quality mindset, communication proficiency, problem resolution