Infant Arockia Raj.M
Lead Engineer Validation
Bangalore
Summary
Pre and post silicon Validation Engineer with expertise in functional validation and automation testing. Developed and executed test plans that significantly improved testing efficiency. Strong analytical skills and collaboration with cross-functional teams resulted in successful project outcomes. Experienced in test content development, toolchain compilers, and IP traffic generators, enhancing overall project performance.
Overview
7
7
years of professional experience
Work History
Lead-Validation Engineer Proxelera Pvt Ltd
AMD
Bangalore
01.2025 - Current
- Contributed to initial phase of Protium & Palladium platform bring-up in pre-silicon.
- Developed automated tool for ASVF framework, executing C-based tests effectively.
- Created compile tool for C test cases, increasing testing efficiency.
- Formulated comprehensive test plan for Functional ADMA IP with features such as SG linked list and interrupt.
- Devised test plan for Security feature SHA and AES, ensuring compliance with customer requirements.
- Supported Integrion team with OSPI flash connectivity to SOC.
SoC Functional Validation Engineer
Intel Technology India Pvt Ltd
Bangalore
06.2022 - 10.2024
- Engineered automation framework to enhance efficiency of data integration checks across use cases.
- Executed comprehensive validation test plan for security, addressing critical system aspects.
- Developed detailed test cases for JESD IP, covering diverse scenarios to ensure functionality.
- Validated 16G and 32G use cases, confirming compatibility with specifications.
- Conducted thorough verification of all use cases using Synopsis Verdi waveform analysis.
- Formulated tailored test plans for various customer use cases, ensuring rigorous validation.
- Played pivotal role in initial security bring-up from FPGA model, establishing foundational measures.
- Contributed to seamless integration of JESD IP and Siemens traffic generator during bring-up activities.
Validation Engineer Moschip Technology Limited
Western Digital
Bangalore
03.2021 - 06.2022
- Analyzed CMC specification documents to ensure comprehensive understanding of requirements.
- Conducted in-depth analysis of clock configurations across all IPs to guarantee synchronization.
- Studied architecture of clock domains, gaining insights into design and interrelationships for validation.
- Developed comprehensive test plan to validate CMC features and ensure compliance with specifications.
- Executed test cases per test plan, verifying CMC performance across various scenarios.
- Implemented functionalities for enable, disable, idle, power down, and force wakeup modes.
- Validated support for external wakeup mode to enhance system response to activation triggers.
- Performed frequency measurement tasks to ensure accurate monitoring of clock frequencies.
Validation Engineer-II
Anvhaya Technical Solutions Pvt. Ltd
Bangalore
06.2018 - 03.2021
- Conducted regression and stress testing across multiple platforms to ensure system stability.
- Configured test cases tailored to specific platform requirements, optimizing overall testing efficiency.
- Implemented additional criteria for test cases, enhancing coverage and accuracy across various platforms.
- Identified failures across all platforms, employing troubleshooting techniques to resolve issues promptly.
- Verified pre-silicon test scenarios, ensuring alignment with project objectives and specifications.
- Prepared detailed test reports documenting results, observations, and recommendations for further action.
- Facilitated discussions with IP owners for failure analysis, promoting effective problem-solving.
Education
B.E - Electronics and Instrumentation Engineering
St. Joseph College of Engineering
Skills
Functional validation and testing
- Test plan development
- Automation frameworks
- C programming skills
- Security and IP validation
- Automation testing strategies
- Product development processes
- Root-cause analysis techniques
- Hardware schematic interpretation
- Traffic generator integration
Timeline
Lead-Validation Engineer Proxelera Pvt Ltd
AMD
01.2025 - Current
SoC Functional Validation Engineer
Intel Technology India Pvt Ltd
06.2022 - 10.2024
Validation Engineer Moschip Technology Limited
Western Digital
03.2021 - 06.2022
Validation Engineer-II
Anvhaya Technical Solutions Pvt. Ltd
06.2018 - 03.2021
B.E - Electronics and Instrumentation Engineering
St. Joseph College of Engineering
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