JAGADISH K

ROLES AND RESPONSIBILITIES:

• Schematic Symbol Creation.
• Schematic Drafting.
• Footprint Creation.
• Footprint mapping for Schematic symbols.
• Netlist Creation
• High speed board layouts designing in the various Industries and domains
• Possess expertise in board stack up analysis, Library management and Impedance driven highly constraint board designing
• Strong in conceptual knowledge on IPC7351 footprint creation, EMI Concepts, Impedance control design, Timing analysis and Fabrication process of HDI boards
• Expertise in designing of DDR, SD RAMs, HDMI, Ethernet, Power Supply, PCI-express, RF designs
• Good knowledge and experience on using complex rules like Spacing, Physical and Electrical length constraint
• Design for EMI/EMC and Compliance Standards
• Generation of CAD data (Gerber file, drill drawing, stack up details), BOM details

PROFESSIONAL EXPERIENCE:

Component Engineering:

• Library creation and QA validation and Library maintenance for Sockets, Discrete’s, IC's, Connectors Other Electrical and Electro Mechanical Components.
• Datasheet download, analysis and creation of Libraries and QA validation as per IPC and various customer’s standard.
• Maintained the part database of over 2 Components.
• Created PCB Libraries with Cadence, Orcad, Altium, Pads Tools.
• Lead a Team of 8 members for a specific customer project

PCB Layout Design:

• Released 20+ PCB’s within 12months in Allegro and Altium
• Experienced in BGA, FBGA and DDR upto 18 layers.

PROJECT DETAILS & DESCRIPTION:

1. BNET-USB BOARD:

• BNET-USB BOARD is 18-layer (100 x 90 mm) PCB in Allegro.
• 823 Symbols, 1386 nets and 2345 Connections.
• Components used BGA and DDR2.
• Minimum conductor width/spacing: 4-mil /4-mils.
• Minimum VIA (hole/Pad):8/16-mils.
• Maintained impedance matching for 40, 50 for SE signals & 80, 90 & 100 for differential pairs.
• Critical on the board- placement and isolations.
• Provided shielding.
• Used power supply +5V, +3.3V, +1.8V.

2.FIREBIRD CPU:

• 405810_7038_LI3_PSB is a 16-layer (120 x 150 mm) PCB.
• 553 Symbols, 846 nets and 1592 Connections.
• Minimum conductor width / spacing: 6-mil / 6-mils.
• Minimum VIA (hole/Pad):08/16-mils.
• High speed lines- LPDDR4, NAND/NOR, FLASH, eMMC, GPS/GNDSS, Cellular Modem, MIPI.
• Power supplies are PMIC, Solar(External), in board LDO’s, 12V battery- 3.3V, 5V, 8V, 12V, 13V, 15V.
• Isolation between Power, Digital and Analog signals.
• Split plane creation for different powers used.

3.BATTERY INTERFACE BOARD:

• 0440673004_Battery Interface Board 4-layer (335.7 x 73.6 mm) RF PCB.
• 427 Symbols, 317 nets and 814 Connections.
• Minimum VIA (hole/Pad):10/20-mils.
• Minimum conductor width/spacing: 8-mil /8-mils.
• Critical considerations-High Voltage(120V).
• Maintained impedance matching 50 ohms for RF and
• 100 ohms for differential pairs.
• Critical considerations for Placement of GSM, Wi-Fi and antennas. Isolations and split grounds, Routing and length matching.

4.INEFNION - CLIENT SUPPORT

• Dedicated Layout Designer for Infineon from Zettaone Technologies
• Designed 12 boards in the last financial year(2023-2024) for Infineon alone(Infineon & Cypress)
• Schematic capture in Altium and Allegro from Hand Sketched/PDF shared by the user
• Most of the Infineon Board are Power boards and DUT with maximum layer count of 6.
• High Power application boards for testing their High power FETs with Voltage over 80V and current rating of 30A.
• Deserializer Board (from Cypress unit)- High speed board with Interface like MIPI, USB, Ethernet and SMA-50.
• Maintained QoD rating of >5.4/6 for all the design which I worked to retain the projects from Infineon every year.
• BOM scrubbing against Infineon database and raise part creation request

PROJECT SUPPORT:

• Client Interaction
• Constrain set-up
• Component Placement.
• Routing, Length matching & Plane Creation.
• Design Review
• Gerber review and Release.