Jaya Easwar R
Physical Design Engineer
Nagercoil,TN
Summary
- Physical Design Engineer with 4.5 years of experience in 4nm, 5nm, 7nm, and 16nm nodes.
- Good analytical skills about overcoming congestion and techniques about optimization in Placement and CTS.
- Strong expertise in analyzing timing reports and resolving design/timing violations.
- Strong background in optimizing design performance, area, and power while meeting timing and verification requirements.
- Have worked on subsystem level covering complete physical design flow from synthesis, STA, placement & routing (PnR), and clock tree synthesis (CTS) to GDS merge and chip finishing.
Overview
4
4
years of professional experience
2
2
Certificates
Work History
Senior Design Engineer
Tessolve Semiconductor Private
10.2024 - Current
- Successfully delivered multiple subsystems to tape-out across advanced nodes.
- Performed subsystem-level partitioning, and provided pin placement feedback with optimized macro placement to improve timing and routability.
- Optimized clock tree design by resolving skew issues, ensuring balanced insertion delay, and improved timing margins.
- Hands-on experience in custom CTS methodologies to address unique clocking challenges, and enhance design performance.
- Hands-on experience in early-stage clock planning for critical subsystems, improving timing margins, and reliability.
- Executed post-route ECOs for timing, functional, and DRC fixes, reducing closure cycle time.
Design Engineer II
Tessolve Semiconductor Private
09.2022 - 10.2024
- Implemented strategies for multi-domain floorplanning and placement, optimizing performance, and reducing congestion.
- Resolved congestion hotspots through iterative floorplan refinement and congestion-driven placement strategies.
- Performed early clocking for memory blocks, achieving minimal skew necessary for robust timing closure.
- Proficient in hotspot analysis and optimization, reducing closure cycle time, and improving QoR.
- Executed timing ECOs while preserving shorts, hotspot integrity during the final ECO stage, achieving clean sign-off.
- Implemented duty cycle correction techniques to minimize jitter and improve clock reliability.
Design Engineer
P2F Semiconductors
08.2021 - 08.2022
- Handled blocks with critical timing requirements, achieving closure across multiple corners and modes.
- Managed critical clock and memory blocks, ensuring minimal skew, and robust timing margins.
- Performed ECOs on critical paths without disturbing final-stage fixes, ensuring a clean sign-off.
- Maintained project timelines by optimizing closure cycle time, and ensuring on-time handoff to integration teams.
Education
B.E - Electrical and Electronics Engineering
Panimalar Institute of Technology
01.2020
Skills
PnR Tools - Synopsys Fusion Compiler, Cadence Innovus
Certification
RV-SKILLS Center for Emerging Technologies
Timeline
Senior Design Engineer
Tessolve Semiconductor Private
10.2024 - Current
Design Engineer II
Tessolve Semiconductor Private
09.2022 - 10.2024
Design Engineer
P2F Semiconductors
08.2021 - 08.2022
RV-SKILLS Center for Emerging Technologies
03-2021
B.E - Electrical and Electronics Engineering
Panimalar Institute of Technology