Project Intern
Semi-Conductor Laboratory
S.A.S Nagar
01.2025 - 07.2025
- Employed Cadence Virtuoso for schematic and layout design tasks related to digital devices, using XOR gate as a practical example to gain industrial insights
- Employed HSPICE for pre- and post-layout simulations, calculating time against functionality performance of digital device in normal, extreme hot, and cold temperature conditions as per industry standards
- Designed and analyzed serial interfaces UART, SPI, and I2C, using open-source VHDL code.
Developed testbenches for each communication protocol to validate functionality.
Compiled source code and testbenches with Synopsys VCS for accurate simulation.
Utilized Synopsys DVE to visualize waveforms and assess signal integrity.
