M. Jebin Vijai
RTL Methodology
Bangalore
Summary
Skilled engineering Leader, with proven track record of building performing engineering teams. Over 19 years of experience in RTL domain working with Mobile,Server,Client,Automotive projects. Committed to rapidly and efficiently completing projects by leveraging team-based frameworks to best leverage available engineering talent. Managed teams across geo's effectively to bring 1+1=3 effect.
Overview
19
19
years of professional experience
Work History
Engineering Manager: Static Check (CDC, RDC, LINT, VCLP, DFT),Constrains,Formal, RTL Power & RTL Quality
Intel Technology India Pvt. Ltd.
6 2018 - Current
- Managing a team of 15 dedicated and dynamic Engineers across the RTL space
- Product development of front-end flow involving more than 40 tools, testing and deployment to bring impact for the entire design community
- Managing the Cloud deployment and support across different Business Units
- Providing methodology leadership to the teams from start of program till completion of design execution focusing on CDC, RDC, SVA Assertion for CDC signoff, Glitch, Lint, Constraints, Formal, VCLP, Power Estimation
- Focus on quality IP collaterals delivery to make sure the SOC integration is seamless
- Established prototypes based on AI to migrate designs to new versions of flow and methodology, enable easier bring up of new projects, quicker and foolproof analysis for CDC ,RDC ,Lint and VCLP
- Exploring new capabilities of vendor tools and deploy them to avoid silicon issues
- Explore opportunities for automation and develop solutions to improve QOR
- Representing the frontend methodology team for Critical server programs for all flows
- Managing multiple vendor engagement for all front-end flows, tool qualifications and deployment.
Application Consultant Functional Verification
Mentor Graphics - Now Siemens
11.2015 - 06.2018
- Managing/owning the CDC activities for India, Asia Pacific for Tier-1/Major Accounts
- Work very closely with the Global Accounts Team
- Proliferation, Deployment and Support of CDC, Gate –CDC ,Reset Domain Crossing
- Delivering Periodic Product updates to Senior Managements and Engineering teams
- Initiated Competitive replacements, migration to new methodologies establishing ROI
- Provide inputs to R&D to enhance the tool and add new features
- Creating dynamic team by mentoring guiding and roadmap establishment.
Sr. Lead Engineer Functional Verification Team
Qualcomm
09.2012 - 09.2015
- Working closely with the DV teams from the start of project to make execution smooth
- Enabling Migrations of Simulators across functional verification, Low Power Simulation
- Bring up the SV Assertion flow and Power Estimation flow of Verdi
- Adding new features and testing QBAR/QVMR – Robust internal flow for Simulation
- Support the Functional verification flow (QBAR/QVMR) across Qualcomm locations
- Collaborating with License Team and IT/LSF Team for effective/speedy solutions
- Onboarding consultants working with Procurement, Legal, Staffing, IT and Facilities
- Training New Users, Advanced usage clarification to Experienced Users / Leads
- Working closely with the Vendors to understand their roadmap and push for enhancements for ROI.
Staff Post Sales Application Engineer –Spyglass Range of Products
Atrenta - Now Spyglass
06.2011 - 09.2012
- Manage Customer Interaction at Texas Instruments, Bangalore
- One point Product support on Sypglass products Viz., Spyglass, Spyglass Base (Lint ,Advanced Lint) ,Spyglass CDC, Spyglass Constraints, Spyglass DFT, Spyglass Low Power and Spyglass Power Estimation and TI specific products - TIPM, Detector
- Enabling adoption of new Methodologies -CDC Abstraction flow and Products on customer environment
- Providing periodic feedback to the Product team and working very close with R&D
- Periodic trainings to new users and advanced users on new features
- Scoping meeting with champion users before and during production runs
- Continuous interaction with the Methodology team to streamline the flow scripts.
Consulting Application Engineer (CAE)-Spring Soft Products Certitude and Verdi
CMR Design Automation
09.2007 - 05.2011
- Functional Qualification - Certitude: Manage multiple Tier 1 Accounts
- Providing feedbacks on strategic planning and decision making
- Introducing Certitude to customers and prospects for the first time
- Initiating, Scheduling, carrying out and monitoring evaluation at customer sites
- Deploying of Certitude at customer premises, integrating into flow seamlessly
- Monitor the usage, fine-tune the usage and above all win customers
- Updating the new features and educating the users on ROI by Luncheon session
- Validate customer requests for enhancements and update R&D
- Periodic marketing events at customer sites and remotely as situation demands
- Debug Automation & Visibility Enhancement: Novas Products – Verdi & Siloti: Introducing the products/new features to new users and prospects
- Showcasing the various debug techniques to automate and speed up debug
- Conducting mundane technical session to educate the customers to validate ROI
- Demonstrate the new features like SV assertion evaluator, SV test bench debug
- Introduce power aware debug for UPF/CPF, Siloti on customer environments
- Monitor, fine tune usage, periodic customer support
- Providing Customer requirements and enhancements requirements to R&D.
Verification Engineer
PMC-Sierra
07.2006 - 08.2007
- Tachyon – QE8: Understanding the functional test plan
- Writing tests to verify the new frame steering functionality of Tachyon
- Understand/modify the existing checking mechanism and Monitor coverage.
Design Engineer
Sasken Communication Technologies
07.2005 - 07.2006
- Functional verification of AMBA APB – UART Bridge using Specman: Framed the test plan, generated test cases, implemented input and output bfms, written scoreboard, checkers and monitors and obtained good coverage
- Modeling and verification of UART: Done behavioral modeling of UART in Verilog, created the test plan, written test benches, test cases in Verilog and verified the design for all scenarios.
Education
HSC -
Good Shepherd Matriculation Higher Secondary School, Marthandam
SSLC - undefined
Good Shepherd Matriculation Higher Secondary School, Marthandam
B.E. - ECE -
Sri Ram Engineering College, University of Madras
M.Tech VLSI Design -
Vellore Institute of technology
Skills
RTL, CDC,RDC, Constraints Verification, Formal, RTL Power Estimation, Flow Architecture, Development, Validation and Release Management
Technical Forums
- IEEE CAS (Circuit and Systems) Bangalore Chapter Contributor
- Accellera CDC working group to come up with a standard for CDC/RDC collaterals
Papers Presented
- DAC 2022 - Left Shift of Multi-Cycle Paths and False Paths Signoff by Formal and Dynamic Simulation Methodologies with significant ROI
- DAC 2020 - 1. Catching Re-spin Glitches at Clock Trees, Reset Trees and CDC Paths. 2. Vclp Debug Systems: Foolproof VCLP Signoff
- DVCON - 2019 - Our experience of Glitches on Clock Trees, CDC paths and Rests Trees
- SNUG - 2019 - Stretching the limits? Faster hierarchical CDC analysis with parallel signoff
- SNUG - 2015 - DPPM Reduction by GATE RTL Correlation
- SNUG - 2014 - Interrogating Formal Environment
- IOY – 2013 - Objective Verification Closure
- QBUZZ - 2013 - Coverage Number Generation and Objective Verification Closure
Self Evaluation
Fast Learner, Collaborative, Customer Centric, Cool and Supple, Optimistic and a firm believer of dreams.
Personal Information
- Pan Number: ALVPM2880J
- Age: 42
- Passport Number: Z6647707 (DOE 28/03/32)
- Date of Birth: 06/05/82
- Gender: Male
- Nationality: Indian
- Marital Status: Married
Languages
Tamil
Kannada
Telugu
Malayalam
Hindi
Timeline
Application Consultant Functional Verification
Mentor Graphics - Now Siemens
11.2015 - 06.2018
Sr. Lead Engineer Functional Verification Team
Qualcomm
09.2012 - 09.2015
Staff Post Sales Application Engineer –Spyglass Range of Products
Atrenta - Now Spyglass
06.2011 - 09.2012
Consulting Application Engineer (CAE)-Spring Soft Products Certitude and Verdi
CMR Design Automation
09.2007 - 05.2011
Verification Engineer
PMC-Sierra
07.2006 - 08.2007
Design Engineer
Sasken Communication Technologies
07.2005 - 07.2006
Engineering Manager: Static Check (CDC, RDC, LINT, VCLP, DFT),Constrains,Formal, RTL Power & RTL Quality
Intel Technology India Pvt. Ltd.
6 2018 - Current
HSC -
Good Shepherd Matriculation Higher Secondary School, Marthandam
SSLC - undefined
Good Shepherd Matriculation Higher Secondary School, Marthandam
B.E. - ECE -
Sri Ram Engineering College, University of Madras
M.Tech VLSI Design -
Vellore Institute of technology
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