Jeena Samuel
ADOOR
Summary
Dynamic Project Engineer at the Centre for Development of Advanced Computing, with expertise in RTL design and microprocessor development. Skilled in Bluespec System Verilog and FPGA verification, with a strong aptitude for problem-solving, and team leadership. Dedicated to achieving excellence through innovative, high-quality design solutions.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Project Engineer - RTL Design
Centre for Development of Advance Computing
Trivandrum
08.2022 - Current
- Working on the Digital India RISC-V Microprocessor Development Program by developing the microprocessor series called VEGA Processors.
- Designing, enhancing, and functionally validating a 64-bit, 16-stage quad-core processor (AS4161-Processor) through compilation and simulation of Decode and Commit pipeline stages.
- Performed functional verification of design through emulator testing, bitstream generation, and STING test for FPGA board assessment.
- Implemented modifications based on thorough evaluation of design pre-synthesis and timing reports.
Education
Masters of Technology - VLSI & EMBEDDED SYSTEMS
ER & DCI IT - CDAC
THIRUVANANTHAPURAM07-2022
Bachelor of Technology - Electronics And Communication Engineering
Sree Narayana Institute of Technology
Adoor, Pathanamthitta07-2019
Skills
- Programming proficiency: Bluespec System Verilog, intermediate in Verilog, basics of VHDL, Python, C, and C
- Technical skills: RTL design, microprocessor development, simulation analysis, FPGA verification, and hardware debugging
- Key strengths: strong work ethic, reliability and dependability, problem-solving ability, strong leadership skills
Languages
Malayalam
First Language
English
Advanced (C1)
C1
Hindi
Elementary (A2)
A2
Certification
- Successfully completed certification training in 'Advanced VLSI Design' conducted by Maven Silicon at C-DAC, Trivandrum.
- Successfully completed the NPTEL certification course in Advanced Computer Architecture.
- Attended 38th International Conference on VLSI Design & 24th International Conference on Embedded Systems-2025 at Bangalore.
Accomplishments
- Received an award for delivering a technical presentation titled 'The RISC-V Revolution: Disrupting Dominance' at the Science Day event organized by C-DAC
- Honored as the best outgoing student of the Bachelor of Technology program, 2019
Timeline
Project Engineer - RTL Design
Centre for Development of Advance Computing
08.2022 - Current
Masters of Technology - VLSI & EMBEDDED SYSTEMS
ER & DCI IT - CDAC
Bachelor of Technology - Electronics And Communication Engineering
Sree Narayana Institute of Technology
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