JHANSI RANI BOGGAVARAPU
Fresher
Vatsavai,Andhra
Summary
Seeking a design & verification engineer position that enables me to utilize my skills within the field to make a positive contribution to the company. Strengths in verilog and system verilog backed by training & projects.
Overview
6
6
years of post-secondary education
Education
High School Diploma With 96.3% - Mathematics,Physics,Chemistry
Sri Chaitanya Bharathi Junior College
Vijayawada, Andhra Pradesh, IndiaMasters With 5.3/6 GPA - Electrical And Computer Engineering
Carleton University,
Ottawa, Ontario 09.2018 -
Bachelors of Technology With CGPA : 9.19 /10 - Electronics And Communication Engineering
Gandhi Institute of Technology And Management
Visakhapatnam ,Andhra Pradesh 06.2014 -
Secondary School (10th) With 9.5/10 -
Sri Chaitanya Techno School
PenuganchiproluTraining For Functional Verification - Vlsi Design And Verification
Vlsiguru Institute
Bangalore,Karnataka 09.2020 - Current
Skills
Programming Languages: C, C (Basics), Data Structures (Basics),Matlab
Hardware Description & Verification Language: Verilog, VHDL, System verilog
Software, Circuit Simulator, Tools: MS Office, MS Word, MS PowerPoint,Top Spice, H Spice, P Spice, Cadence Virtuoso, Linux, Modelsim, Questasim, Edaplayground
Personal Traits: Strong communication skills, with the ability to convey complex technical concepts to other peers in verbal and written form Fluent English (both written and spoken)
Knowledge in Ethernet - an advantage Solid understanding of developing system level test cases and ASIC Design Flow
Knowledge of SystemVerilog experience with code coverage, functional coverage, formal verification tools Strong execution orientation FluenDemonstrated ability to work independently as well as in a multi-disciplinary group environment
Projects
Using VERILOG
Interrupt Controller, SPI Controller, UART, Synchronous and Asynchronous Fifo
Using SYSTEM VERILOG
Ethernet packet loopback design verification
AXI VIP Development using SystemVerilog
Memory Controller Functional Verification using System Verilog
Paper Publication
Paper published on "Performance Analysis of Embedded System for Data Acquisition on FPGA."
Link: https://www.springer.com/us/book/9789811305139 (pages 409-416).
Internship
In Questease Solutions on "Implementation of low power pulse triggered flip-flop design using Static CDFF and CDFF."
Timeline
Training For Functional Verification - Vlsi Design And Verification
Vlsiguru Institute
09.2020 - Current
Masters With 5.3/6 GPA - Electrical And Computer Engineering
Carleton University,
09.2018 -
Bachelors of Technology With CGPA : 9.19 /10 - Electronics And Communication Engineering
Gandhi Institute of Technology And Management
06.2014 -
Secondary School (10th) With 9.5/10 -
Sri Chaitanya Techno School
High School Diploma With 96.3% - Mathematics,Physics,Chemistry
Sri Chaitanya Bharathi Junior College