JHANSI RANI BOGGAVARAPU

Seeking a design & verification engineer position that enables me to utilize my skills within the field to make a positive contribution to the company. Strengths in verilog and system verilog backed by training & projects.

Using VERILOG

Interrupt Controller, SPI Controller, UART, Synchronous and Asynchronous Fifo

Using SYSTEM VERILOG

Ethernet packet loopback design verification

AXI VIP Development using SystemVerilog

Memory Controller Functional Verification using System Verilog

Paper published on "Performance Analysis of Embedded System for Data Acquisition on FPGA."

Link: https://www.springer.com/us/book/9789811305139 (pages 409-416).

In Questease Solutions on "Implementation of low power pulse triggered flip-flop design using Static CDFF and CDFF."