Jitendra Kumar

Low Power Methodology

• Utilized EDA tools such as Cadence Innovus and Synopsys PTPX to perform comprehensive vectorless and vector-based power analysis and validate power optimizations.
• Analyzed dynamic power for lower nodes in-depth.
• Created automation to perform vectorless power estimation at different views in Innovus.
• Performed power analysis and experiments based on slew, load, and extraction corner updates.
• Performed wire-cap and load-cap analysis to debug dynamic power.
• Created automation for memory power analysis and experimented to save total dynamic power in no-operation mode of memory.
• Hand-on experience on vector-based power analysis on 5nm designs.
• Performed correlation between vector and vector-less approaches of power calculation.
• Worked on debugging low annotation of switching activity.

Physical Design

• Strong understanding in RTL2GDSII flow or design implementation in leading process technologies.
• Good understanding of RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Good automation skills in TCL, tool specific scripting.
• Strong understanding of DRC (Design Rule Check), LVS (Layout versus Schematic) extraction, and tech files.