JITENDRA KUMAR

• Driven Layout Design Engineer with almost 3 years at Intel, mastering lower tech nodes including 10nm, 7nm, 5nm, and 18A technologies, and excelling in cross-functional collaboration. Achieved first-pass layout design quality through expertise in DRCs, LVS, ERC, antenna violations, matching, shielding, and various physical verification signoff flows before Tapein . Always recognized by cross-site stakeholders for my exceptional quality of work and on-time delivery.

TECHNOLOGY DEVELOPMENT DEPARTMENT AWARD(2024)

Zhyiong Ma(VP ,Intel TD),

Link:https://pdf.ac/2nH207

• VITUOSO XL,CALIBRE,GPDS,ASSURA,FUSION COMPILER,PRIMETIME

SUPER MIM CAP LAYOUT DESIGN ACHIEVING CAP DENSITY OF (397fF/um2 )  FIRST TIME IN P1276 FOR VARIOUS INTEL PRODUCTS TO MINIMIZE VOLTAGE DROOP AND POWER STABILITY FOR IFS CUSTOMERS

.Designed various 3 plate stacked MIM capacitors of different sizes with largest size equals to 1.16mm2 made up of small MIM cap tiles 64400um2

.Done the floorplanning in collabs with  device integration team for minimizing the area and to ensure the  appropriate connections for all the 3 plates

.Cleaned DRCs,LVS,ERC ,Antenna violations along with various signoff checks before Tapein and get recognized by my cross site stake holders for quality of the work

DESIGN LAYOUT FOR VARIOUS ANTIFUSE/FUSE ARRAYS FOR MEMORY APPLICATIONS IN INTEL 18A PROCESS WITH BACKSIDE POWER DELIVERY NETWORK

.Designed layout of sub-blocks like analog comparator and analog mux used in antifuse design.

.Done the  common centroid/ interdizitization matching for various transistors and  also splitting of transistors wherever necessary to minimize process variations

.Biggest challenge faced are the mitigation of  antenna violations because of high voltage  design requirements greater than 4.8v

.Done the shielding for critical signals along with DRCs clean,LVS and connectivity checks before signing off

DESIGNED LAYOUT OF VARIOUS TEST STRUCTURES  ON INTEL PROCESS 1274,1276,X76FVA TO MITIGATE LATCHUP AND ELECTROMIGRATION  ISSUES  TO INCREASE  PRODUCT RELIABILITY

.Base to front end layers connectivity are done manually and total 10 connections in earlier LU structures are   minimized to 3 connections vcc,vss,io as per the requirements.I have to update metal stacks from M7 to M18 in compliance with all the design rules of intel4.

.In X80A (INTEL 14A)I am involved in designing layout of various type of EM structures like shortline,line dominant,standard,via dominant with fixed via enclosure and line cd length for testing product TTF and ensuring it is greater than product lifetime

.Done the custom Routing and connectivity of backside metal structures with pads because of no automation support

INTEL INTERNAL MENTORSHIP PROGRAM IN PHYSICAL DESIGN(JAN2024-AUG2024)

• Logic synth, PPA basics for implementation (constraints/timing basics, timing opt basics, power estimation/opt basics, area opt basics etc.)
• FEV basics/VCLP basics for implementation, Scan basics,Floorplan/powerplan, Physical synth/placement, congestion analysis, LV/PDN basics
• CTS Theory, Clock Tree analysis, Setup/hold timing analysis
• Advanced concepts ocv/aocv/pocv, derates, crpr, margins, xtalk, debugging/fix strategies,ECO basics, ECO flow, min-max fixes,Data Integrity checks, Static IR result interpretation; Dynamic IR result interpretation & debug for violations; RV checks
• Understanding of various Power optimization techniques and In-depth Understanding of power estimation flow. Hands on learning on different power reports and power analysis.

I hereby declare that the above-mentioned details are true to the best of my knowledge and belief.