Joy Jeniffer

Senior Physical Design Engineer with extensive experience at Wafer Space, excelling in high-performance floor planning, and automation using Tcl. Expertise in achieving SOC FV sign-off through innovative low-power strategies. Strong collaborator, adept at resolving complex design challenges while ensuring design integrity and efficiency.

• Project 1 : With Google on their cutting-edge Cu-5nm/3nm technology. My responsibilities included managing a complex netlist-to-GDSII flow, conducting extensive block-level floorplanning iterations, resolving constraint issues, and optimizing timing post-CTS. I also experimented with VT cell usage variation and defined power domain utilization targets. I tackled block-level DRVs by strategically upsizing cells, splitting fan-outs, and adding buffers on critical nets. Additionally I also supported bugs and regressions wrt silicon implementation flow.
• Project 2 : With NVIDIA on Cu-7nm/10nm/14nm technology. My responsibilities included managing three crucial blocks, each consisting of 141 macros and 1 million standard cells, 68 macros and 0.7 million standard cells, and 19 macros and 0.8 million standard cells. I utilized advanced tools like Innovus, ICC2, TopPlanner, ICV, and Pinnaco to excel in the netlist-to-GDS II flow, block-level floorplanning, power planning, pre-placed cell placement, placement and routing, detailed routing, IR drop and power EM issues, DRCs checks, antenna fixing, timing fixes, crosstalk, and signoff fixes.
• Project 3 involved working on Qualcomm's Cu-5nm, 7nm, and 11nm technologies My responsibilities included Verifying over 75 design blocks, each containing more than 1 million standard cells. And Ensuring block-level logic equivalence and SOC FV sign-off. Using Cadence Conformal LEC to identify and resolve logic equivalence issues. Adding instance equivalences, pin constraints, and renaming rules to maintain a clean design Maintaining a DFT constraints file and running batch mode for all hard macros to prevent SOC issues.Optimizing runtime for SOC-level runs by exploring different mapping and flattening options
• Project 4 : With Graphene, Cu-28nm Technology, with 13 macros and a standard cell count of 28k. My initial utilization was 70.9%, and the frequency was set at 125MHz with a rectangular shape. I was responsible for block-level physical design, power planning, decap placement, placement-driven synthesis, detailed routing, DRC checks, LVS checks, antenna fixing, and timing fixes, all alongside formal verification.

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• Father's Name: A. Francis
• Mother's Name: C. Pushpa
• Date of Birth: 02/22/94