Jyothinath C

RTL to GDS implementation of two blocks. It includes Synthesis, Floorplan, power-grid generation, place & route, clock tree synthesis and timing closure

Design Details: Technology - Intel 10nm Tools: ICC2,Primetime & ICV

• Synthesis and PnR Engineer for multiple Blocks of FUSE subsystem from netlist to GDS and coming with recipes and methodologies for power, performance and area
• Solved Setup & hold critical paths through FUSE IP pins by building clock trunks to create clock divergence
• Setup critical repeater flop placement are corrected for ECO partitions and clocks trunks are built manually at ECO stages
• Clock push & pulls experiments at eco stages for timing critical paths
• CTS Trails for Latency reduction and timing closure for the Boundary flops for critical Interface
• Assisted on Forward Clocking for Channel Partitions with stringent skew requirement by building a manual clock trunk
• Developed multiple TCL scripts to check the placement of certain physical only cells at SOC level at a particular distance , Antenna cell insertion , Power recovery (VT Swap) in non critical timing paths & VSS opens correction for Shield nets

RTL to GDS implementation of two blocks. It includes Synthesis, Floorplan, power-grid generation, place & route, clock tree synthesis and timing closure

Design Details: Technology - TSMC 7nm Tools: ICC2,Primetime & Caliber

• Effectively leaded for subsystem of 8 blocks also handled one of timing critical block in same subsystem
• Worked as a team for low power and timing issues for all the blocks in subsystem
• Worked with RTL and sign-off teams and given timely feedback to RTL , timing (FC STA) , PV & power teams for better QOR achievement.
• Completed all blocks on time with good quality and also helped blocks of other subsystem for timing closure
• Developed tcl scripts to trace the repeater flops and bound flops placement for better timing

RTL to GDS implementation of two blocks. It includes Synthesis, Floorplan, power-grid generation, place & route, clock tree synthesis and timing closure

Design Details: Technology - Intel 10nm Tools: ICC2,Primetime & ICV

• Synthesis and PnR Engineer for multiple Memory Controller Blocks from netlist to GDS and coming with recipes and methodologies for power, performance and area.
• Congestion and timing issues are resolved with better placement options like placement blockages , cell padding & path groups .
• CTS experiments to meet latency requirements by skew groups , Multi point CTS and Push & pull experiments for timing closure.
• Low power issues like missing level shifter and ISO cells are resolved with tcl scripts by splitting fanouts and update ISO strategies for DFT signals

RTL to GDS implementation of two blocks. It includes Synthesis, Floorplan, power-grid generation, place & route, clock tree synthesis, fixing DRC & LVS, and timing closure

Design Details: Technology - TSMC 7nm Tools: ICC2,Primetime & Caliber

• Timing issues in synthesis resolved by doing SPG [place aware synthesis],path groups ,boundary optimization and flattening of few modules by taking feedback from designer
• Physical cell placement and MACRO placement issues are resolved with different floorplan experiments to meet TSMC 7 floorplan guidelines.
• Timing and Congestion issues w.r.t Voltage region placement are fixed with proper port &module placement. Communication between modules and ports are analyzed, ports and voltage regions are placed accordingly also placement experiments like path grouping and partial blocks are implemented to meet timing and congestion issues.
• Had Skew and Insertion delay issues with Generated clocks. Skew groups created by analyzing communicating flops and also concurrent clock and data optimization are implemented in CTS for better QOR
• PV issues likes DRC & LVS violations are analyzed and fixed

Netlist to GDS implementation of three blocks. It includes Floorplan, power-grid generation, place & route, clock tree synthesis, fixing DRC & LVS, and timing closure

Design Details: Technology - GF7nm Tools: ICC2,Primetime & Caliber

• One of these blocks had issues with balancing the clocks and insertion delays,was able to identify a few points in the clock network that can be excluded while building the clock tree and modified the spec files accordingly, thereby getting the insertion delays under control. This helped me in understanding the complex clock structures and their dependencies
• Have identified several timing related issues and provided feedback regarding a few of them at very early stages which helped in closing the block in expected period of time.
• Other block had congestion issue because of very high AON logic. Was able to control the congestion by exploring some congestion options and Bounding of the relevant logics.

RTL to GDS implementation of two blocks. It includes floorplan,

power-grid generation, place & route, clock tree synthesis, timing ECOs, fixing DRC & LVS, formal verification, crosstalk glitch analysis, and timing closure

Design Details:

Technology - GF14nm Tools: ICC, Primetime, ICV & Formality

• Have done a lot of experiments to reduce the area of the blocks with different utilization values and was able to give feedback regarding the same.
• One of these blocks had a problem with very high logic levels that cannot be reduced from front end team. Was able to control the timing of these paths by controlling the insertion delays and skewing by 2-3 levels (macro modeling).
• Utilization was high so had to take care of this by adding density screens, bounds and several other congestion options

Netlist to GDS implementation of Two block. It Includes Feedthrough Placement,Floorplan, Power Planning, Clock tree Synthesis,Routing, Extraction, Timing Analysis ECO,DRC & LVS

Design Details : 28nm. Tools: IC Compiler, Encounter,Primetime, & Calibre.

• PnR Engineer for two MC Blocks from netlist to GDS and coming with recipes and methodologies for power, performance and area
• Had timing issues related to clock gating paths resolved with bound and skewing experiments