K S ROSHAN KUMAR

RTL Design and Integration

• CPU(generation with respect to spec)/MCU integration with custom IPs' (development as well) in-house SRAM for L1/L2/L3 caches, DFT/MBIST RTL integration and glue logic with LINT/CDC quality checks closure.
• UPF/SDC updates and validation using CLP/Time-vision.
• SOC-level checks: CG-checks, ISO-reset checks, TV-hier checks, GCDC closure.
• Early netlist delivery to back-end using RTLA for PPA/congestion analysis.
• Debug and test plan support for various stages of DV (Func/MVSIM/Presim/Postsim) and Post-silicon debug support as well.
• Functional ECO implementation and LEC sign-off.

Specification & Documentation

• Delivered key specs: CODA, debug monitor, UDI TAP, scan wrapper, power architecture spec, clock tree structure spec, application notes etc.
• Developed xFilter Flow to extract tied/async flops for post-sim via PT/MTBF reports.

IP Design with mirco-architecture development, RTL coding, qc and sign-off

• APB TX-RX 4 phase async bridge based on handshake protocol used for crossing voltage/clock domains.
• N2 SRAM test chip - Designed and implemented architecture for SRAM PPA analysis at N2 node, incorporating configurable register block, in-house SRAM power supply control IP, and Tessent MBIST-generated RTL. Developed and signed off UPF and SDC constraints to ensure power and timing integrity along with necessary verification support.

Key achievements:

• Special Recognition for handling high end little Core used in NVIDIA's latest AI super computer.
• Successfully taped out ~7 projects, including CPU(A55/A76/A725)/MCU design and integration, powering high-performance solutions for TVs and smartphones.
• Mentored junior engineers by providing guidance on best practices and industry standards, fostering professional growth.