SAI KRISHNA KAIRAMKONDA
Hyderabad,
Summary
- Over 8 years in the semiconductor industry, specializing in the transition from RTL Netlist to GDS.
- Expertise in timing closure and signoff processes, ensuring high-quality design outputs.
- Proven track record of enhancing performance metrics and optimizing workflows to drive project efficiency.
- Currently working as Lead CAD Physical Design Engineer at Intel since July 2021(3 years 6 months).
Led the physical design team for a high-performance CPU project's, achieving a 15% improvement in timing closure.
Implemented advanced power optimization techniques, reducing power consumption by 10%.
- 2 years 9 months (Nov 2018 – July 2021) in P&R, including timing closure at L&T Technology Services (Intel and Nvidia).
Successfully completed the physical design of a GPU for Nvidia(GH100), meeting all timing and power targets.
Developed and automated scripts to streamline the P&R process, reducing design cycle time by 20%.
- 2 years (Nov 2016 – Dec 2017) of experience in P&R, including timing closure at SoCtronics Technologies (AMD).
Contributed to the physical design of a high-speed networking chip for AMD, achieving first-pass silicon success.
Optimized the floorplanning and placement strategies, resulting in a 12% area reduction.
- Trained at VEDA IIT for 6 months (May 2016 – Nov 2016), recruited through college placements.
Overview
8
8
years of professional experience
Work History
Sr Lead Physical Design Engineer (CAD)
Intel
Hyderabad
07.2021 - Current
- Leading a team of four engineers in developing and optimizing physical design methodologies and flows, ensuring high-quality deliverables.
- Collaborated with design teams to define architecture, approach, and methodologies for incorporating new features into physical design projects.
- Worked with technology enablement teams to integrate and enhance features required for new projects, aligning with cutting-edge advancements.
- Partnered closely with SoC implementation and physical design teams to ensure seamless project execution.
- Evaluated and validated tool flows for diverse design types across multiple technology nodes to maintain flow robustness and quality.
- Streamlined ticket management processes using JIRA and HSD platforms, optimizing resolution time and resource utilization.
- Assessed technology shifts by running test designs to analyze impacts on area, power, and timing.
- Automated reporting for regression status and run quality, improving efficiency and minimizing errors.
- Developed and integrated CRI (Custom Routing Implementation), MSCTS, SDP, and Mixed Placer to enhance design capabilities.
- Strengthened flow reliability through advanced noise, power, and timing analysis (STA) optimizations.
- Proficient in tools like Cadence Genus, Cadence Innovus, and sign-off tools, leveraging expertise to achieve project goals.
Sr Physical Design Engineer
L&T Technology Services
Bangalore
12.2018 - 07.2021
- Successfully achieved timing closure for P&R projects at L&T Technology Services with leading clients, Intel, and NVIDIA.
- Played a key role in Intel’s Tiger Lake project, managing physical design tasks from floor planning to sign-off.
- Delivered a successful block-level implementation, including placement, CTS, routing, and STA, adhering to stringent power, performance, and area targets.
- Conducted multiple floorplan experiments to optimize area utilization, and improve timing convergence.
- Utilized advanced CTS and routing techniques to ensure robust clock distribution and signal integrity.
- Contributed to NVIDIA’s H100 project by handling complex analog blocks, including PLL, ADC, and ESD macros, and implemented custom analog routing for power and clock using TCL scripting.
- Demonstrated expertise in block-level P&R, encompassing floor planning, placement, routing, and STA, while driving significant performance, power, and area optimizations through innovative design techniques.
- Collaborated with methodology teams and managed two partitions/blocks, developing automation scripts in Tcl/Perl to enhance efficiency.
- Conducted extensive floorplan experiments, placement refinements, and CTS optimizations, alongside implementing IR reduction techniques.
- Ensured DRC and DRV compliance, completing comprehensive design sign-off checks to deliver high-quality results.
Physical Design Engineer
Soctronics Technologies Pvt Ltd
Hyderabad
11.2016 - 11.2018
- Successfully managed the design of two blocks in a Global Foundry (GF) 22nm project, handling approximately 1.2 million instances and achieving a 1.2 GHz operational frequency from floorplanning to GDSII.
- Achieved timing closure at 2.2 GHz through extensive floorplan experiments, advanced CTS optimization, and innovative routing strategies.
- Minimized DRC violations during placement by implementing placement bounds for critical modules and utilizing partial placement blockages in densely packed regions.
- Analyzed and resolved SOC block constraints related to multi-asynchronous and synchronous clocks.
- Addressed and fixed DRC, LVS, and antenna violations, ensuring a robust and clean design.
Education
Diploma - Electronics And Instrumentation Engineering
Government Institute of Electronics
HyderabadB.tech - Electronics And Communications Engineering
Institute of Engineers of INDIA
Kolkata,West BengalB.Tech - Engineering Technology
Birla Institute of Technology And Science (BITS)
Pilani,GoaM.tech - MicroElectronics
Birla Institute of Technology And Science (BITS)
Pilani,GoaSkills
- Worked on the latest technology nodes: 18A, 20A, 2nm, 5nm, 6nm, 22nm, and 16nm for Intel, TSMC, Samsung, and GF foundries
- Expertise in FloorPlan, Powerplan, Placement, CTS, Routing, STA, and ECO fixing techniques
- Expertise in static timing analysis using PT and Tempus
- Mastery in scripting languages: TCL, SHELL, and PERL
- Experience in multi-voltage design flows and low-power techniques
- Experience in automation, flow development, CAD, and methodology
- Good with PV checks, LVS, DRC, Antenna, DFM, and ESD analysis
- Experience in EM and IR drop analysis and fixes
- Very good knowledge of CAD algorithms in the physical design space
- Participate in developing methodologies, flow automation, and improvements on existing flows to increase productivity
Accomplishments
- intel - DIVISIONAL RECOGNITION AWARD.
- Recognized for Developing and Enabling a well segregated and scalable SDP Feature in global flow.
Publications
- DAC 2023 - Optimal MSCTS Driver duplication for improved H-Tree Clock Skew and Insertion delay
Timeline
Sr Lead Physical Design Engineer (CAD)
Intel
07.2021 - Current
Sr Physical Design Engineer
L&T Technology Services
12.2018 - 07.2021
Physical Design Engineer
Soctronics Technologies Pvt Ltd
11.2016 - 11.2018
Diploma - Electronics And Instrumentation Engineering
Government Institute of Electronics
B.Tech - Engineering Technology
Birla Institute of Technology And Science (BITS)
M.tech - MicroElectronics
Birla Institute of Technology And Science (BITS)
B.tech - Electronics And Communications Engineering
Institute of Engineers of INDIA
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