Summary
Overview
Work History
Education
Skills
Core Competencies
Certificates And Training
Languages
Timeline
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Kanan Subramanium Nadar

Tirunelveli

Summary

Detail-oriented professional with nearly 3 years of front-end ASIC/FPGA design experience in the service-based industry. Demonstrated expertise as an RTL Design Engineer at Chipspirit Technologies Pvt Ltd, showcasing proficiency in micro-architecture design to RTL sign-off, lint, CDC, RDC, timing closure, leading to seamless integration of complex SoC. Collaborate effectively with cross-functional teams including DV, AMS, DFT, PD team for smooth tape-out and project completion. Experienced in mixed-signal digital design, closely collaborating with the analog team to define interface boundary and timing. Currently working on a mixed-signal chip in the 55nm node. Successfully developed security IP for product ABHED1.

Overview

3
3
years of professional experience

Work History

RTL Design Engineer

Chipspirit Technologies Pvt Ltd
07.2022 - Current

Project 3: Hammerhead ASIC Design

5/2023 – Present

  • Role: Lead Developer
  • Description: Led the design and implementation of a mixed signal chip ASIC.
  • Technologies Used: Verilog, System Verilog, VHDL.
  • Achievements:
  • Designed LVDS IP.
  • Integrated DW Synopsys IP, performed CDC and lint checks.
  • Worked with DV team to create test cases
  • Collaborated with PD team for timing closure.
  • Worked with analog team on mixed signal digital design.
  • Leadership: Led the project, ensuring successful completion and integration.
  • Outcome: Delivering a high-performance mixed signal chip ASIC that met design specifications and client requirements.

Project 2: Security IP development for client product

11/2022- 02/2023

  • Role: Developer and Mentor
  • Description: Developed security IP using Diffie-Hellman algorithm for client-customized product
  • Technologies Used: Verilog, System Verilog, FPGA
  • Achievements: Enhanced security protocol efficiency and ensured compatibility with USB-based systems.
  • Collaboration: Coordinated with client and internal teams to ensure smooth integration.
  • Outcome: Delivered a customized security IP solution that met client requirements and improved overall system security.

Project 1: Development of Security IP for Cryptography Product

7/2022- 02/2023

  • Role: Developer
  • Description: Designed and implemented advanced security IP to enhance data protection and integrity in cryptography products.
  • Technologies Used: Verilog, System Verilog, FPGA, AES, RSA
  • Achievements: Improved data encryption speed by 30% and reduced power consumption by 20%.
  • Collaboration: Worked with the system team to ensure seamless integration of security features.
  • ·Patent: Received patent (Patent Title: System, apparatus and method for hardware-based cryptography, Patent Number: 557199).
  • Outcome: Successfully delivered a robust security IP that was integrated into the company's flagship cryptography products.

Digital Repair Service

Reliance SMSL Pvt Ltd
10.2020 - 02.2022
  • Supporting device care team, pre-launch testing and after sale support
  • Achievements: Recognized as the best performer at both regional and state levels

Education

Bachelor of Engineering (B.E.) - Electronics and Communication

Shantilal Shah Govt Engineering College
Bhavnagar, Gujarat
09-2020

Skills

  • HDL: Verilog, System Verilog
  • Protocol: AXI4, IIC, SPI, UART
  • Quality check: Lint, CDC, RDC
  • Tools: Xcelium, Questa Sim, Model Sim, Vivado, Spyglass, Quartus prime, Virtuoso, Emac

Core Competencies

  • ASIC/FPGA design
  • Architecture design
  • RTL coding
  • IP design
  • SoC integration
  • Linting
  • CDC fixes
  • Test plan creation
  • Debug design issue
  • Functional ECO
  • Silicon validation support

Certificates And Training

Design and Verification training, Maven

02/2022 – 07/2022, 

Completed comprehensive training in design and verification, 

Project: Router 1x4, 

Tools: Questa Sim, Quartus Prime, Gvim, 

Language: Verilog, System Verilog, 

Concepts: FIFO, FSM, Architecture design

Languages

Tamil
English
Gujarati
Hindi

Timeline

RTL Design Engineer

Chipspirit Technologies Pvt Ltd
07.2022 - Current

Digital Repair Service

Reliance SMSL Pvt Ltd
10.2020 - 02.2022

Bachelor of Engineering (B.E.) - Electronics and Communication

Shantilal Shah Govt Engineering College
Kanan Subramanium Nadar