Detail-oriented professional with nearly 3 years of front-end ASIC/FPGA design experience in the service-based industry. Demonstrated expertise as an RTL Design Engineer at Chipspirit Technologies Pvt Ltd, showcasing proficiency in micro-architecture design to RTL sign-off, lint, CDC, RDC, timing closure, leading to seamless integration of complex SoC. Collaborate effectively with cross-functional teams including DV, AMS, DFT, PD team for smooth tape-out and project completion. Experienced in mixed-signal digital design, closely collaborating with the analog team to define interface boundary and timing. Currently working on a mixed-signal chip in the 55nm node. Successfully developed security IP for product ABHED1.
Project 3: Hammerhead ASIC Design
5/2023 – Present
Project 2: Security IP development for client product
11/2022- 02/2023
Project 1: Development of Security IP for Cryptography Product
7/2022- 02/2023
Design and Verification training, Maven
02/2022 – 07/2022,
Completed comprehensive training in design and verification,
Project: Router 1x4,
Tools: Questa Sim, Quartus Prime, Gvim,
Language: Verilog, System Verilog,
Concepts: FIFO, FSM, Architecture design